SoC Core Overdrive Control for Fast Vehicle Boot Activation
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Solution Overview
Problem
Complex System-on-Chip (SoC) processors face challenges in meeting stringent boot time requirements within a cost-effective and stress-minimal manner, particularly in environments like vehicles where subsystems need to be operational within a short time, such as less than 100 ms, due to demanding operating conditions.
Innovation Solution
Implementing an overdrive manager that dynamically controls clock frequency and voltage to selectively execute code using a subset of processor cores at a higher power level during high-speed activation, then switching to a lower power level after the activation interval, thereby reducing boot time without excessive stress on components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If clock frequency is dynamically increased to provide higher performance during boot-up, then boot time is reduced, but power consumption and thermal stress increase
Solution Approach 1:
The system dynamically adjusts clock frequency based on operational phase: during boot-up, frequency is increased above maximum operational frequency to accelerate initialization, then automatically reduced to normal operational frequencies once boot is complete. This dynamic frequency scaling resolves the contradiction by applying high power only when necessary for reducing boot time, then transitioning to lower power consumption mode.
Solution Approach 2:
The patent changes the clock frequency parameter temporarily during boot-up operations, allowing the processor to operate at frequencies higher than its maximum rated operational frequency. This parameter change enables faster boot times while the system monitors and controls the duration of high-frequency operation to manage power consumption and thermal effects.
2Speed
If clock frequency is increased above maximum operational frequency, then boot speed improves, but component stress and reliability decrease
Solution Approach 1:
The system employs periodic frequency adjustment: brief intervals of high-frequency operation during boot-up are followed by transitions to normal operational frequencies. This periodic cycling between high and normal frequencies allows the system to achieve fast boot speeds while giving components time to dissipate heat and recover, thereby maintaining reliability.
Solution Approach 2:
The system prepares for high-frequency operation by ensuring adequate thermal management infrastructure is in place before boot-up begins, and limits the duration of high-frequency operation to prevent excessive thermal accumulation. This beforehand cushioning approach allows the system to safely exploit high-frequency performance without compromising long-term component reliability.
3Productivity
If all processor cores are activated during boot-up, then system readiness is achieved faster, but power consumption increases
Solution Approach 1:
The boot-up process is segmented into phases, with critical system initialization performed first on essential processor cores, followed by progressive activation of additional cores as needed. This segmentation allows the system to achieve minimum viable readiness faster with lower power consumption, then scale up to full multi-core operation when power budget permits and additional functionality is required.
Data Source
AI summary
Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.