SoC Parallel Image Correction Shared Memory
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Solution Overview
Problem
Current system on chip designs for image sensing devices are not optimized for reduced area, which can lead to increased power consumption and manufacturing costs.
Innovation Solution
A system on chip with a shared memory that performs multiple image processing tasks in parallel, generating correction values for pixel data through different processing methods and selecting the most appropriate value for output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple image processing operations are performed sequentially, then processing completeness is improved, but processing time and power consumption increase
Solution Approach 1:
The image processing system is divided into multiple independent processing units (first image processing unit, second image processing unit, third image processing unit), each performing a specific correction operation. This segmentation allows parallel execution of processing tasks, reducing total processing time and power consumption while maintaining processing completeness through the coordinated operation of specialized units.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by adding a temporal dimension to the processing architecture. Multiple processing operations are executed simultaneously across different time periods, transforming the processing model from one-dimensional sequence to multi-dimensional parallel execution, thereby reducing overall processing time and energy consumption.
2Reliability
If multiple image processing operations are performed sequentially, then processing completeness is improved, but processing time increases
Solution Approach 1:
The image processing system is divided into multiple independent processing units (first image processing unit, second image processing unit, third image processing unit), each performing a specific correction operation. This segmentation allows parallel execution of processing tasks, reducing total processing time while maintaining processing completeness through the coordinated operation of specialized units.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by adding a temporal dimension to the processing architecture. Multiple processing operations are executed simultaneously across different time periods, transforming the processing model from one-dimensional sequence to multi-dimensional parallel execution, thereby reducing overall processing time.
3Measurement precision
If separate processing units are used for each image processing operation, then processing quality is improved, but device complexity increases
Solution Approach 1:
A shared memory unit is introduced that serves all processing units for storing and accessing image data. This universal memory structure reduces device complexity by eliminating the need for separate dedicated memory for each processing unit, while maintaining processing quality through the coordinated access patterns and data management mechanisms implemented in the control unit.
Solution Approach 2:
The control unit acts as an intermediary that coordinates the operations of multiple processing units and manages data access to the shared memory. This intermediary structure simplifies the overall system architecture by centralizing control logic and data management, reducing the complexity that would otherwise arise from direct peer-to-peer communication and coordination between processing units.
4Device complexity
If a shared memory is used for all processing operations, then device complexity is reduced, but memory access time increases
Solution Approach 1:
The control unit performs preliminary actions by pre-managing memory access sequences and coordinating read/write operations before actual processing occurs. This preliminary coordination optimizes memory access patterns, reducing conflicts and wait times between processing units, thereby minimizing the time penalty of shared memory access while maintaining the architectural simplicity of the shared memory design.
Data Source
AI summary
A system on chip and method for operating a system on chip are provided. A system on chip includes a shared memory configured to store image data and a processor configured to: generate a first correction value by performing first image processing for a first pixel value of a first pixel of the image data received from the shared memory, generate a second correction value by performing second image processing, which is different from the first image processing, for the first pixel value of the image data received from the shared memory, generate a third correction value by performing third image processing, which is different from the first image processing and the second image processing, for the first pixel value of the image data received from the shared memory, and output a first pixel correction value that is changed from the first pixel value by comparing the first to third correction values with the first pixel value and selecting one of the first to third correction values.