SoC Partitioning with Interposer for Cost-Effective Metal Layer Stacking
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Solution Overview
Problem
The increasing complexity of system-on-chip (SoC) designs with multiple metal layers of varying dimensions leads to high production costs due to the need for advanced processing of all layers, where not all components require such advanced processing, resulting in inefficient use of resources and increased costs.
Innovation Solution
A method of partitioning SoC components into groups based on process node, power consumption, processing speed, and cost criteria, followed by sorting higher and lower level metal layers into separate stacks for cost-effective electrical connection using an interposer and through-substrate vias, allowing for shared routing and reduced processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all metal layers are processed with advanced process nodes to accommodate complex SoC designs, then design flexibility and component integration are improved, but production cost increases significantly
Solution Approach 1:
The patent divides the SoC design into multiple partitions, each with its own process node requirements. Different partitions can be manufactured using different process nodes (e.g., 7nm for high-performance computing, 28nm for memory), allowing cost optimization while maintaining design flexibility. This segmentation enables each partition to be processed according to its specific performance requirements rather than forcing all layers to use the most advanced process node.
Solution Approach 2:
The patent applies different process nodes to different spatial regions (partitions) of the SoC based on local performance requirements. High-performance computing partitions use advanced process nodes (7nm), while memory or I/O partitions use less advanced but more cost-effective nodes (28nm). This local quality approach ensures that advanced processing is applied only where necessary, reducing overall production costs while maintaining design adaptability.
2Ease of manufacture
If multiple partitions with different process nodes are integrated into a single SoC, then production cost is reduced, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The patent introduces an interposer as an intermediary layer that facilitates integration between partitions manufactured with different process nodes. The interposer provides standardized interfaces and routing that bridge the different process node partitions, simplifying the integration process. This mediator approach manages the complexity of multi-node integration by providing a uniform interface layer that handles the heterogeneity of underlying partitions.
Solution Approach 2:
The patent resolves integration complexity by transitioning from planar integration to three-dimensional stacking. Different process node partitions are stacked vertically rather than placed side-by-side in the same plane. This dimensional change allows independent optimization of each partition while simplifying inter-partition connections through vertical vias and interposer layers, effectively managing integration complexity.
3Ease of manufacture
If higher level metal layers with larger pitch are removed from advanced process chips, then production cost is reduced, but electrical connection complexity increases
Solution Approach 1:
The patent merges the routing functions of removed higher-level metal layers with the interposer structure. The interposer incorporates redistribution layers and via structures that combine multiple routing functions into a unified intermediate structure. This merging approach maintains electrical connectivity while allowing the chip to use fewer metal layers, reducing manufacturing cost while managing connection complexity through the interposer's integrated routing solution.
Data Source
AI summary
A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.