Automatic Pin Multiplex Verification for SOC Chip Design
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Solution Overview
Problem
The increasing complexity of SOC chips and limited number of pins lead to a significant workload and errors in manual verification, low reusability of verification code, and potential omission of design defects due to incomplete pin verification.
Innovation Solution
A method and device for automatically verifying full chip pin multiplexing, which includes obtaining pin information, generating an automatic verification process, and executing a test sequence and check sequence to verify all pins simultaneously, reducing the workload and improving verification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual verification is used to verify chip pin multiplexing, then verification can be performed, but the workload is significant and errors occur frequently
Solution Approach 1:
The verification system performs self-verification by automatically generating verification code from pin multiplexing configuration information. The system verifies its own pin multiplexing correctness without external manual intervention, thereby reducing workload and improving reliability through automated self-checking mechanisms.
Solution Approach 2:
Manual mechanical verification operations are replaced by an automated electronic verification system. The system uses computer-based automatic code generation and execution to substitute human manual verification, eliminating human errors and significantly reducing the time and effort required for verification.
2Adaptability or versatility
If verification code is modified in batches to adapt to changing design requirements, then pin function changes can be accommodated, but the workload increases significantly
Solution Approach 1:
The verification system is designed to be dynamic and adaptive. It automatically adjusts verification code based on changing pin multiplexing configurations without requiring manual batch modifications. The system dynamically generates updated verification code whenever design requirements change, maintaining high adaptability while preserving verification efficiency.
Solution Approach 2:
The system handles parameter changes in pin multiplexing configurations by automatically detecting and adapting to these changes. When pin functions or multiplexing parameters are modified, the verification system automatically generates updated verification code with the new parameters, eliminating the need for manual batch code modifications and maintaining high productivity.
3Ease of operation
If only multiplex pins are checked during verification, then the verification process is simplified, but design defects may be omitted
Solution Approach 1:
The verification system performs multiple verification functions simultaneously. It verifies not only multiplex pins but also non-multiplex pins and detects connection errors between different pins. This universal verification approach ensures comprehensive defect detection while maintaining operational simplicity through automated multi-function verification.
Solution Approach 2:
The system implements comprehensive feedback mechanisms that monitor all pins including multiplex and non-multiplex pins. The verification process provides feedback on connection errors and design defects across the entire pin set, ensuring no defects are omitted while keeping the verification process simple through automated comprehensive checking.
4Adaptability or versatility
If the number of pins is increased to meet functional requirements, then chip functionality is improved, but erroneous association between pins occurs
Solution Approach 1:
The verification system acts as an intermediary to detect and prevent erroneous pin associations. It automatically verifies pin multiplexing configurations and connection relationships, identifying association errors before they affect chip functionality. This intermediary verification layer ensures reliable pin associations even as the number of pins increases to meet functional requirements.
Data Source
AI summary
Embodiments of the present disclosure provides a method and a device for automatically verifying full chip pin multiplex, equipment, and a storage medium. The method comprises obtaining pin information that comprises a pin functional attribute and pin multiplex information; generating an automatic verification process for pins based on the pin information; and automatically verifying the pins one by one according to the automatic verification process generated for the pins. Hence, the system can reduce the workload of verification, improve verification efficiency, and reduce omission of vulnerabilities.