SoC Power Management Unit Clock and Regulator Control
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Solution Overview
Problem
Current methods for reducing power consumption in System on Chip (SoC) are inadequate, particularly in minimizing leakage current during sleep states, and existing hardware solutions either fail to completely shut down or require time-consuming initialization, leading to ongoing power consumption.
Innovation Solution
An SoC architecture that includes a clock unit, CPU, main regulator, and restoration processor, where the Power Management Unit (PMU) stops clock provision and powers off the main regulator, storing and restoring register information using an auxiliary regulator that consumes less power, allowing efficient transitions between sleep and active states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a retention register is used to store present state by using data retention power, then data can be retained during sleep state, but the register size becomes almost two times larger than a general register and leakage current continues to consume power
Solution Approach 1:
The system divides the power management into two independent parts: a main regulator that powers down completely during sleep state, and an auxiliary regulator that remains active to power only the retention register. This segmentation allows data retention functionality to be isolated from the main system, enabling the main regulator to be fully powered down while maintaining minimal power consumption for data preservation.
Solution Approach 2:
Power is selectively applied only where needed during sleep state. The auxiliary regulator provides localized power to the retention register while the main regulator is completely powered down. This local quality approach ensures that power consumption is minimized by providing electricity only to the specific component (retention register) that requires it for data preservation, rather than maintaining power to the entire system.
2Loss of energy
If the main regulator is completely powered off during sleep state, then power consumption is minimized, but the system requires time-consuming reset and initialization when powered on again
Solution Approach 1:
The system performs preliminary action by storing the state of all registers before the main regulator is powered down. The retention register captures and preserves the present state data in advance of the power-off event. When power is restored, this pre-stored data is immediately available, eliminating the need for time-consuming initialization and reset operations, as the system can quickly restore operation using the preserved state information.
3Adaptability or versatility
If a software control method is used to manage power consumption, then flexibility is maintained, but CPU operation and program memory usage increase power consumption
Solution Approach 1:
The system replaces the software-based control mechanism with a hardware-based solution. Instead of using CPU operations and program memory to manage power states, the patent implements a dedicated hardware circuit with an auxiliary regulator that automatically manages power transition. This hardware substitution eliminates the need for continuous CPU intervention and program memory access during power management, significantly reducing power consumption while maintaining control functionality.
Data Source
AI summary
An apparatus and method for reducing power consumption in a System on Chip (SoC) are provided. The SoC includes a clock unit for providing clocks to all elements included in the SoC, a Central Processing Unit (CPU) for controlling the SoC to perform designated functions, a main regulator for supplying power provided from an external battery to remaining elements included in the SoC other than a PMU, and a restoration processor for storing, in the PMU, registration information on the CPU and all peripherals included in the SoC when a transition from an active state to a sleep state is made. The PMU stops provision of a clock from the CPU by controlling the clock unit for stopping provision of all clocks by controlling the clock unit and for controlling the main regulator to be powered off when the restoration processor, wherein the PMU requests the restoration processor to store the registration information, completes the register information storing, when the transition from the sleep state to the active state is made.