SOC Power Management Unit Activity-Based State Control
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Solution Overview
Problem
Modern semiconductor chips face challenges in managing power consumption efficiently, leading to increased heat dissipation costs and performance degradation due to inefficient resource management across multiple processing units within a system-on-a-chip (SOC).
Innovation Solution
A power management unit (PMU) within the SOC determines activity levels across different processing units, adjusts their power-performance states, and allocates thermal design power (TDP) to maintain optimal power consumption while prioritizing performance by limiting high power states in less active units and boosting active ones, ensuring the SOC operates within its thermal design power limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software control is used for management of on-die resources, then resource management capability is improved, but response time increases due to inherent software delay
Solution Approach 1:
A hardware-based power management unit (PMU) is introduced as an intermediary between the processors and the operating system. The PMU monitors processor activity levels and autonomously adjusts power states without requiring software intervention, thereby eliminating software delays while maintaining effective resource management.
Solution Approach 2:
The patent replaces the software-based control mechanism with a hardware-based control mechanism. The PMU uses hardware circuits to monitor processor activity and control power states, substituting the mechanical/software execution model with a direct hardware control model that operates without instruction execution delays.
2Productivity
If individual processor power states are optimized independently, then individual processor efficiency is improved, but overall SOC power management efficiency deteriorates
Solution Approach 1:
The patent merges the power management control of multiple processors into a single unified hardware PMU. The PMU simultaneously monitors activity levels of all processors and coordinates their power states to optimize overall SOC power consumption, rather than allowing independent optimization that misses system-wide opportunities.
Solution Approach 2:
The PMU is designed as a universal power management unit that handles multiple processor types (CPU, GPU, DSP, etc.) with different activity characteristics. It applies unified power management policies across diverse processors, adapting to each processor's specific workload while maintaining system-wide optimization.
3Productivity
If high P-state is selected for memory bounded workloads to increase utilization, then processor utilization is improved, but power efficiency deteriorates due to inefficient operation at high power state
Solution Approach 1:
The PMU dynamically adjusts processor power states based on real-time activity level monitoring. For memory-bounded workloads, the PMU detects that the processor is waiting on memory operations and automatically reduces the power state, adapting the power consumption to the actual computational demand rather than maintaining a fixed high state.
Solution Approach 2:
The PMU implements continuous feedback monitoring of processor activity levels. When the activity level falls below a threshold (indicating the processor is stalled waiting for memory), the PMU responds by reducing the power state. This feedback loop ensures power states match actual workload demands, improving power efficiency without sacrificing utilization.
Data Source
AI summary
A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.