SoC Power Estimation Using Probabilistic Bit Switching

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Solution Overview

Problem

Conventional power estimation methods for System on Chip (SoC) assume all bits switch simultaneously, leading to pessimistic power calculations that do not account for the decreasing probability of all bits switching together, resulting in increased power consumption as SoC capacity increases.

Innovation Solution

A probability-based method calculates the minimum number of bits that can switch without error across the SoC's warranty time period, using binomial probability calculations and error correction mechanisms to determine the actual number of bits that switch, thereby reducing power estimation to conserve power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional power estimation methods assume all bits switch simultaneously, then power calculation is simplified, but power consumption increases due to pessimistic calculations

Engineering Contradiction:

Improvepower calculation complexityVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent changes the parameter from assuming all N bits switch simultaneously to calculating the actual minimum number of bits NP that can switch without error based on probability. This parameter change resolves the contradiction by using statistical methods to determine realistic switching bit counts, thereby reducing pessimistic power estimates while maintaining calculation feasibility through probabilistic models.

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If the number of bits N increases to increase SoC capacity, then storage capacity improves, but power consumption increases linearly

Engineering Contradiction:

Improvestorage capacityVSAvoidpower consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by calculating only the minimum necessary number of bits NP that actually need to switch simultaneously based on probability, rather than assuming all N bits switch. This allows the system to achieve the required storage capacity N while consuming power proportional to the actual switching bits NP, which is less than N for large N values.

Inventive Principle:

Principle #16Partial or excessive action

3Use of energy by moving object

If probability-based calculation is used to determine actual switching bits, then power efficiency improves, but calculation complexity increases

Engineering Contradiction:

Improvepower efficiencyVSAvoidcalculation complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent performs preliminary probability-based calculations during the design phase to determine the minimum switching bits NP for given parameters (warranty period, data rate, error correction). This preliminary action resolves the contradiction by establishing NP upfront, avoiding complex real-time probability calculations during operation, and enabling simplified power estimation using the pre-determined NP value.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10560116B2Probability-based optimization of system on chip (SOC) power

Publication Date: 2020.02.11 SEAGATE TECH LLC

AI summary

A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.