SoC Power Domain Segmentation for CPU-Accelerator Integration
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Solution Overview
Problem
Existing hardware accelerators and CPUs are separate components on different substrates, relying on off-chip communication techniques like PCIe, which limits data transmission efficiency and integration.
Innovation Solution
A system on a chip (SoC) with hardware accelerators and CPUs integrated on the same chip, utilizing on-chip communication and dividing circuitry into different power or clock domains to enable dynamic power management, allowing idle components to be powered down while others remain operational.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware accelerator and CPU are separate components on different substrates, then device complexity is reduced and ease of manufacture is improved, but data transmission speed and communication efficiency deteriorate
Solution Approach 1:
The patent merges the CPU and hardware accelerator onto a single substrate (SoC), creating an integrated system where the CPU core, hardware accelerator, and memory are co-located. This integration eliminates the need for external communication interfaces like PCIe, enabling direct on-chip communication pathways that significantly increase data transmission speed while managing complexity through unified system architecture.
Solution Approach 2:
The patent transitions from a distributed multi-substrate architecture to a centralized single-substrate architecture, fundamentally changing the spatial dimension of system organization. This dimensional shift from off-chip to on-chip integration creates new communication pathways and reduces signal transmission distance, directly improving data transmission speed.
2Use of energy by moving object
If entire hardware accelerator is powered down to save energy, then power consumption is reduced, but ability to quickly resume operations deteriorates
Solution Approach 1:
The patent segments the hardware accelerator into multiple independent power domains, allowing selective power management of different functional blocks. Each power domain can be independently powered down or kept operational based on workload requirements, enabling fine-grained power control that reduces overall power consumption while maintaining quick resume capability for active domains.
Solution Approach 2:
The patent implements dynamic power management where power domains can be flexibly activated or deactivated based on real-time operational needs. This dynamic control allows the system to optimize power consumption by powering down idle domains while maintaining readiness in domains that may need immediate operation, balancing energy savings with resume time requirements.
3Productivity
If entire hardware accelerator remains powered on to maintain readiness, then ability to quickly start operations is improved, but power consumption increases
Solution Approach 1:
The patent divides the hardware accelerator into segmented power domains that can be independently managed. This segmentation allows the system to maintain operational readiness in only the necessary domains while powering down others, achieving a balance between productivity and power consumption by keeping essential functions active and non-essential functions dormant.
Solution Approach 2:
The patent applies different power states to different local regions (power domains) of the hardware accelerator based on their specific operational requirements. Critical domains maintain powered-on states for immediate operation, while non-critical domains are powered down, creating local quality variations in power management that optimize both readiness and energy efficiency.
4Productivity
If CPU and hardware accelerator are integrated on same chip, then communication efficiency is improved, but manufacturing complexity and chip area increase
Solution Approach 1:
The patent combines the CPU and hardware accelerator on a single chip substrate, creating a compact integrated system. This merging eliminates the need for external communication interfaces and inter-chip connections, dramatically improving communication efficiency by enabling direct on-chip data pathways between the CPU and hardware accelerator components.
Solution Approach 2:
The patent employs a nested architecture where the hardware accelerator is integrated within the same chip substrate as the CPU, with memory and other components nested in hierarchical layers. This nesting approach maximizes space utilization and creates efficient communication pathways through short interconnect distances, improving productivity while managing chip area constraints.
Data Source
AI summary
Embodiments herein describe a hardware accelerator that includes multiple power or clock domains. For example, the hardware accelerator can include data processing engines (DPEs) which include circuitry for performing acceleration tasks (e.g., artificial intelligence (AI) tasks, data encryption tasks, data compression tasks, and the like). The DPEs are interconnected to permit them to share data when performing the acceleration tasks. In addition to the DPEs, the hardware accelerator can include other circuitry such as an interconnect, a controller, address translation circuitry, etc. The DPEs may be in a first power or clock domain while the other circuitry is in a second power or clock domain. That way, when the DPEs are idle (e.g., the hardware accelerator currently has no tasks assigned to it), the first power or clock domain can be powered down while the second power or clock domain can remain powered.