SoC Power Domain Segmentation for Standby Energy Reduction

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Solution Overview

Problem

Handheld digital devices face challenges in reducing standby power consumption while maintaining quick resume capabilities and minimizing active power consumption during user application execution, due to limitations in power management techniques for central processing units and the trade-offs between low-power and low-performance processors.

Innovation Solution

A programmable System on a Chip (SoC) with optimized power domains and power islands, where each power domain has a dedicated voltage rail and power islands can be power-gated or clock-gated to minimize leakage current, allowing only necessary functional blocks to be active based on the specific device functionality required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If the CPU is powered down during standby mode to reduce power consumption, then standby power consumption is reduced, but the ability to quickly resume full power operation is compromised

Engineering Contradiction:

Improvestandby power consumptionVSAvoidresume speed from standby

Core Design Contradiction:

Use of energy by stationary objectVSSpeed

Solution Approach 1:

The patent divides the integrated circuit into multiple power domains (first power domain and second power domain) that can be independently controlled. The first power domain includes CPU and instruction fetch/decode circuits, while the second power domain includes execution circuits. This segmentation allows selective powering down of the execution circuit during standby mode while keeping the CPU and control circuits powered, enabling quick resume without full system reinitialization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different parts of the circuit have different power management characteristics. The patent applies power gating at the domain level, allowing the execution circuit to be completely powered down while the control circuit remains active. This local quality approach optimizes power consumption in the standby state while maintaining the ability to quickly resume full operation by simply reactivating the execution domain.

Inventive Principle:

Principle #3Local quality

2Use of energy by stationary object

If low-power processors are used to reduce power consumption during active mode, then power consumption is reduced, but processor performance deteriorates

Engineering Contradiction:

Improveactive power consumptionVSAvoidprocessor performance

Core Design Contradiction:

Use of energy by stationary objectVSProductivity

Solution Approach 1:

The patent implements dynamic power management by switching between different operational modes. During active mode, the entire circuit is powered to achieve high performance. During standby mode, the execution circuit is powered down to reduce consumption. The system dynamically adjusts its power state based on operational requirements, allowing it to achieve both low power consumption during idle periods and high performance during active periods.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system periodically transitions between active and standby modes. During standby, only essential circuits remain powered. When wake-up events occur, the system periodically activates additional power domains as needed. This periodic action allows the system to maintain low average power consumption while ensuring high performance is available when required.

Inventive Principle:

Principle #19Periodic action

3Speed

If functional blocks are kept active to ensure quick resume from standby, then resume capability is improved, but power consumption increases

Engineering Contradiction:

Improveresume speed from standbyVSAvoidstandby power consumption

Core Design Contradiction:

SpeedVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the essential control functions into a separate first power domain that remains active during standby. The execution circuit is extracted into a separate second power domain that can be completely powered down. This extraction allows the system to maintain minimal functionality for quick resume while eliminating unnecessary power consumption from the execution domain during standby.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The control circuit and CPU are kept in a preliminary active state during standby mode, prepared for quick resumption. The execution circuit is not activated in advance but can be rapidly powered up when needed. This preliminary action approach ensures the system is ready for quick resume without maintaining high power consumption continuously.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9411390B2Integrated circuit device having power domains and partitions based on use case power optimization

Publication Date: 2016.08.09 NVIDIA CORP

AI summary

A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.