SoC Power Gating Controller for Rush-In Current and Wake-Up Timing
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Solution Overview
Problem
Existing power-gated IC designs face challenges in minimizing the size of customized libraries of cells required to support wide-ranging restrictions on wake-up time and rush-in current characteristics, leading to inefficiencies in power control systems.
Innovation Solution
A rush-in current controller is introduced, comprising a clock module and a ring oscillator module that provide a delayed sleep control signal based on counting preset clock and ring oscillator cycles, connected between an unswitched power supply and a virtual power supply line, allowing for staged switching of header or footer cells to manage rush-in currents during wake-up and sleep operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple customized header/footer cells and delay buffers are used to support wide-ranging wake-up time and rush-in current restrictions, then the power control system can accommodate various IC applications, but the library size and device complexity increase significantly
Solution Approach 1:
The patent implements a universal power control mechanism where a single header cell and single footer cell can be dynamically controlled to serve multiple IC applications with different wake-up time and rush-in current requirements. The delay buffer and control logic enable these cells to adapt their behavior based on application-specific parameters, eliminating the need for multiple customized cell libraries while maintaining support for diverse power gating scenarios
Solution Approach 2:
The patent introduces dynamic control of header/footer cells through delay buffers that can be configured with different delay times. This dynamic adjustment allows the same physical cells to exhibit different effective strengths and switching characteristics, enabling adaptation to various rush-in current and wake-up time requirements without requiring physically different customized cells for each application
2Object-generated harmful factors
If larger header/footer cells are used to reduce rush-in current, then rush-in current characteristics improve, but wake-up time increases and IC area is consumed
Solution Approach 1:
The patent applies preliminary action by using delay buffers to control the timing of when header/footer cells are activated. Instead of directly switching large cells that would cause rush-in current, the system first introduces a controlled delay period during which the power supply voltage ramps up gradually. This preliminary voltage establishment prevents inrush current while still enabling wake-up functionality, and the delay can be configured to balance between current control and wake-up speed requirements
Data Source
AI summary
A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.