Multi-Core SoC Power Gating with Shared Rails for DVFS
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Solution Overview
Problem
Existing system on chip (SoC) designs face challenges in efficiently managing power across multiple cores, leading to increased power consumption and heat generation, especially when not all cores are actively performing tasks.
Innovation Solution
The proposed SoC design incorporates multiple cores with independent power gating switches and a power switch that allows connection to both power rails, enabling dynamic voltage and frequency scaling (DVFS) per core, thereby optimizing power usage based on core activity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores are integrated in one processor to improve computing performance, then productivity increases, but power consumption increases
Solution Approach 1:
The power management system is segmented into individual power gating switches for each core, allowing independent power control. Each core has its own power gating switch that can be turned on or off based on activity, enabling selective power delivery to only the cores that need to operate, thus reducing overall power consumption while maintaining multi-core processing capability
Solution Approach 2:
The power gating switches are dynamically controlled based on core activity status. When a core becomes inactive, its power gating switch is turned off to stop power supply, and when activated, the switch turns on to restore power. This dynamic adaptation allows the system to optimize power consumption in real-time according to actual computing needs
2Loss of energy
If power gating switches are added to each core for independent power control, then power management efficiency improves, but device complexity increases
Solution Approach 1:
The power gating switches are designed with a unified control mechanism that can manage multiple cores through a standardized interface. The control logic can issue universal power gating commands that apply to any core, reducing the need for separate complex control circuits for each core and simplifying the overall power management architecture
Solution Approach 2:
Multiple power gating control functions are merged into a single integrated control unit that can manage all cores. By combining the control logic and using shared control signals, the system reduces the complexity that would otherwise arise from having completely independent control circuits for each power gating switch
Data Source
AI summary
A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.