SoC Power Delivery With Adaptive Voltage Headroom Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power delivery systems for systems-on-chip (SoC) guarantee sufficient voltage headroom by setting the voltage regulator high, leading to avoidable power losses and potential SoC malfunctions due to unpredictable current increases.
Innovation Solution
Implementing a distributed adaptive clocking scheme with per core voltage regulators, droop detectors, and frequency controllers to independently throttle core clock signals and adjust voltage set points in response to headroom violations or droops, reducing power loss and preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage regulator voltage is set high to guarantee sufficient voltage headroom at the transistor level for the entire range of SoC load current, then voltage headroom is sufficient, but power losses increase
Solution Approach 1:
The patent implements dynamic voltage scaling by continuously monitoring the actual voltage headroom at the transistor level and adjusting the voltage regulator output voltage in real-time. Instead of using a fixed high voltage setting, the system dynamically adapts the voltage to the minimum required level, thereby maintaining sufficient headroom while minimizing power losses. This is achieved through feedback control mechanisms that modulate the regulator voltage based on actual load conditions and headroom measurements.
Solution Approach 2:
The system changes the voltage regulator output voltage parameter dynamically based on operating conditions. By monitoring load current, transistor voltage headroom, and power loss metrics, the system adjusts the regulator voltage parameter to optimal values that satisfy headroom requirements while minimizing energy loss. This parameter adaptation allows the system to operate efficiently across different load scenarios rather than being constrained to a conservative fixed voltage setting.
2Loss of energy
If the voltage regulator voltage is set low to reduce power losses, then power loss decreases, but voltage headroom may become insufficient leading to SoC malfunctions
Solution Approach 1:
The patent employs feedback control by continuously monitoring the actual voltage headroom at the transistor level and using this information to adjust the voltage regulator output. The system measures the difference between the regulator output voltage and the minimum required transistor voltage, then feeds this headroom information back to the regulator control logic. This feedback mechanism ensures that the voltage is maintained at sufficient levels to prevent malfunctions while avoiding unnecessarily high voltage settings that would increase power loss.
Solution Approach 2:
The system performs self-adjustment by autonomously monitoring its own operating conditions and automatically correcting voltage levels as needed. The voltage regulator incorporates built-in sensing and control logic that enables it to self-regulate the output voltage based on actual headroom requirements, eliminating the need for external intervention or conservative fixed settings. This self-service capability allows the system to optimize its own power efficiency while maintaining reliability.
3Reliability
If conventional power delivery apparatuses guarantee sufficient voltage headroom for the entire range of SoC load current, then voltage headroom is maintained, but avoidable power losses occur
Solution Approach 1:
Instead of applying excessive voltage headroom across the entire load current range, the system applies only the partial or minimum necessary headroom at any given moment. By monitoring actual load conditions and transistor voltage requirements, the system provides just enough voltage margin to ensure reliability, avoiding the excessive voltage application that causes avoidable power losses. This partial action approach optimizes the trade-off between headroom guarantee and power efficiency.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttling operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.