SoC Power Mode Selection Using Parallel Hardware Evaluation
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Solution Overview
Problem
Existing power management techniques for system-on-chip (SOC) rely on high-level software solutions that are time-constrained and require static input conditions, leading to inefficiencies in power state transitions and management.
Innovation Solution
Implementing programmable and reconfigurable hardware-based power management circuitry that performs concurrent evaluations based on multiple criteria to determine optimal power modes, accommodating dynamic changes in SOC states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high-level software solutions are used for power management, then power state transitions can be implemented, but latency issues and time constraints occur
Solution Approach 1:
The patent replaces software-based power management with hardware-based power management circuitry. The hardware circuitry directly monitors SOC state and controls power mode transitions without software intervention, eliminating the time delays associated with software execution and context switching. This substitution of mechanical/hardware control for software control resolves the latency issue while maintaining ease of operation through automatic hardware-driven transitions.
2Device complexity
If static input conditions are required for power management, then simplified control logic is achieved, but adaptability to dynamic SOC states is reduced
Solution Approach 1:
The patent implements dynamic adaptability through hardware circuitry that continuously monitors multiple SOC state parameters and automatically adjusts power modes in real-time. The power management circuitry evaluates current SOC state against predefined criteria and dynamically transitions between power modes without requiring static input conditions. This dynamic hardware-based control maintains relatively simple control logic while achieving high adaptability to changing SOC states.
3Speed
If hardware-based power management is implemented, then latency is reduced and real-time control is achieved, but device complexity increases
Solution Approach 1:
The patent segments the power management functionality into distinct hardware modules: state monitoring circuitry, criteria evaluation logic, and power mode control circuitry. Each module performs a specific function independently, allowing for optimized design of each segment while maintaining overall system simplicity. The segmented architecture enables fast real-time control through dedicated hardware paths while distributing complexity across multiple specialized components rather than one complex monolithic structure.
Data Source
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AI summary
Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.