Adaptive Power Multiplexing for SOC Voltage Drop Reduction
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Solution Overview
Problem
Conventional power multiplexing architectures experience significant voltage drops across memory blocks in series, leading to inefficient power distribution and increased power consumption.
Innovation Solution
Placing power multiplexors proximate to memory blocks, such as within memory channels, to reduce the number of memory blocks powered in series, thereby minimizing voltage drops and improving power distribution efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power multiplexors are placed at the periphery of the SOC to provide power to multiple memory blocks in series, then device complexity is reduced, but voltage drop increases quadratically
Solution Approach 1:
The power distribution network is segmented into multiple independent power domains, each with its own power multiplexor placed close to the memory blocks it serves. This segmentation breaks the long series power path into shorter segments, reducing the voltage drop in each segment while maintaining overall system functionality.
Solution Approach 2:
The patent transitions from a single-dimensional series power distribution approach to a multi-dimensional power distribution architecture. Power multiplexors are distributed throughout the SOC in a two-dimensional layout, allowing power to be delivered through multiple parallel paths rather than a single series path, thereby reducing voltage drop.
2Loss of energy
If power multiplexors are placed proximate to memory blocks to reduce voltage drop, then voltage distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The power multiplexors are designed with universal functionality to handle multiple power supply voltages and control signals. Each multiplexor can selectively connect to different power domains and memory blocks, reducing the need for specialized circuitry and minimizing overall device complexity despite the distributed architecture.
Solution Approach 2:
The power multiplexors are integrated within the memory channel structure, nesting the power distribution function within the existing memory interface architecture. This nesting approach allows power multiplexors to be placed close to memory blocks without adding significant external complexity to the overall device.
3Reliability
If voltage is raised at some components to compensate for voltage drop, then power delivery reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by providing different voltage levels to different regions of the SOC based on their specific needs. Memory blocks receive appropriate voltage levels locally through dedicated power multiplexors, eliminating the need to raise voltage globally. This ensures reliable power delivery to each component without unnecessarily increasing power consumption across the entire device.
Solution Approach 2:
The power distribution system is made dynamic through the use of controllable power multiplexors that can adaptively switch between different power domains based on operational requirements. This dynamic control allows the system to optimize voltage delivery in real-time, maintaining reliability while minimizing power consumption by only raising voltage where and when needed.
Data Source
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Figure 3A
AI summary
A system on chip (SOC) comprising: first memory block and a second memory block; a processing unit coupled to the first memory block and the second memory block; a first power multiplexor disposed between the first memory block and the second memory block and coupled to a first power rail configured to provide an operating voltage to both the first memory block and the second memory block; and enable logic circuitry disposed at a periphery of the SOC away from the first memory block and the second memory block, the enable logic being coupled to control terminals of the first power multiplexor.