SoC Power Path Controller Voltage Selection
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Solution Overview
Problem
System-on-chip (SoC) devices face challenges in reducing power consumption while ensuring operation stability of memory cores, as the minimum power supply voltage required by memory cores is higher than that for logic units, and existing power management systems require multiple power sources and supply lines, leading to inefficiencies.
Innovation Solution
A power path controller is introduced in the SoC, coupled to a first power source with dynamically changing voltage and a second power source with a minimum constant voltage, using switches and a comparator to selectively supply the appropriate voltage to the memory core, while sharing the second power source among multiple controllers to reduce complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple power sources and supply lines are used to ensure memory core operation stability, then the minimum power supply voltage requirement is met, but the power management system complexity increases
Solution Approach 1:
The patent merges the second power source supply lines by making them shared among multiple power path controllers. Instead of providing separate second power source connections to each controller, a single shared supply line serves multiple controllers, reducing the overall number of power supply lines while ensuring memory cores receive adequate power voltage through the selective switching mechanism.
Solution Approach 2:
The second power source is designed with universal functionality, serving both as a backup power source for memory cores and as a shared resource for multiple power path controllers. This multi-functional approach allows the same power source to support multiple memory cores through different controllers without requiring dedicated supply lines for each.
2Reliability
If multiple power sources are used to supply power to memory cores, then the minimum voltage requirement is met, but the number of power sources and supply lines increases
Solution Approach 1:
The patent combines multiple second power source supply lines into a single shared supply line that serves multiple power path controllers. This merging approach reduces the quantity of power supply lines while maintaining the ability to guarantee minimum voltage to memory cores through the comparator-based selective switching mechanism.
Solution Approach 2:
Instead of physically duplicating second power source connections for each controller, the patent uses a shared supply line that effectively 'copies' the power delivery function to multiple controllers through the switching network, reducing the actual number of physical connections required.
3Ease of operation
If separate second power sources are allocated to each power path controller, then each controller has dedicated power supply, but the power consumption and system complexity increase
Solution Approach 1:
The patent merges separate second power source allocations into a shared power source configuration. Multiple power path controllers draw power from a common second power source through shared supply lines, reducing overall power consumption while maintaining controller operational independence through the selective switching mechanism controlled by voltage comparisons.
4Use of energy by moving object
If dynamic voltage adjustment is applied to logic blocks, then power consumption is reduced, but the memory core may not receive sufficient voltage
Solution Approach 1:
The patent segments the power supply management into two independent but coordinated paths: one path dynamically adjusts voltage for logic blocks to reduce their power consumption, while the other path independently ensures adequate voltage delivery to memory cores through the second power source and comparator-based switching. This segmentation allows each memory core to receive sufficient voltage regardless of logic block power saving measures.
Solution Approach 2:
The power path controller acts as an intermediary between the dynamically adjusted logic block power supply and the memory core power supply. It monitors voltage levels and selectively switches between power sources, ensuring that memory cores receive adequate voltage even when logic blocks operate with reduced voltage for power savings.
Data Source
AI summary
A power path controller included in a system-on-chip (SoC) is provided. The power path controller is coupled to a first power source and a second power source. The power path controller includes a first switch located between the first power source and a memory core included in the SoC, a second switch located between the second power source and the memory core, a comparator configured to compare a first power supply voltage supplied from the first power source with a second power supply voltage supplied from the second power source, and a switch controller configured to selectively activate the first switch or the second switch according to a comparison result of the comparator.