Multi-Core SoC Power Rail Switching for Per-Core DVFS
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Solution Overview
Problem
Current System on Chip (SoC) designs face challenges in optimizing power management for multiple cores, as they often require a single voltage regulator to supply maximum currents to all cores, leading to inefficiencies in power consumption and increased area requirements due to the need for higher current capacities and passive devices.
Innovation Solution
The implementation of a System on Chip (SoC) with multiple cores, each having a dedicated voltage regulator and power gating switches, allowing for per-core dynamic voltage management and frequency scaling, which reduces power consumption by selectively connecting cores to power rails based on their operational states and workloads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single voltage regulator supplies maximum currents to all cores, then all cores can operate at maximum performance, but power consumption increases and area requirements increase
Solution Approach 1:
The patent divides the power supply system into multiple independent voltage regulators, each dedicated to specific cores. This segmentation allows each regulator to supply power only to active cores rather than all cores, reducing total power consumption while maintaining performance of active cores.
Solution Approach 2:
The patent implements dynamic power management where voltage regulators can be selectively enabled or disabled based on core activity. Power gating switches dynamically connect or disconnect power rails to cores, allowing the system to adapt power consumption to actual workload requirements.
2Productivity
If a single voltage regulator supplies maximum currents to all cores, then all cores can operate at maximum performance, but area requirements increase due to higher current capacities and passive devices
Solution Approach 1:
By segmenting the power supply into multiple regulators with smaller current capacities, the total area is reduced. Each regulator handles only the current needed for its assigned cores, eliminating the need for large current-capacity regulators and associated large passive devices.
Solution Approach 2:
Multiple smaller voltage regulators are merged to collectively power all cores, replacing the need for a single large regulator. This approach reduces the area required for passive devices while maintaining the ability to supply sufficient current to active cores.
3Use of energy by moving object
If dedicated voltage regulators are implemented for each core, then power consumption is reduced through selective power gating, but device complexity increases
Solution Approach 1:
The patent creates a modular power management architecture where each voltage regulator and power gating switch combination can serve multiple functions - powering different cores at different times. This universality manages complexity by creating repeatable, standardized power delivery units.
Data Source
AI summary
A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.