SoC Power-Up Sequencing With Isolation Signals Across Power Domains
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Solution Overview
Problem
Integrated circuit devices with multiple power domains face challenges during power-up, including unstable operations, contention currents, and noise coupling due to different ramp rates of power supplies, which can lead to damage and increased power consumption.
Innovation Solution
A consolidated power-on-reset system (PORS) is implemented, utilizing level shifter circuits, voltage detection circuits, glitch filter circuits, and logic gates to generate isolation signals, controlling power transitions and reducing noise coupling by enabling or disabling power domains sequentially, thereby managing multiple power domains comprehensively during power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple power domains are supplied simultaneously during power-up, then power-up time is reduced, but contention currents and noise coupling increase causing unstable operation
Solution Approach 1:
The patent applies preliminary action by detecting voltage levels of different power domains before enabling level shifters. The voltage detection circuit monitors each power domain and only enables level shifters when source and destination power domains are both stable, preventing contention currents and noise coupling while maintaining efficient power-up sequencing
Solution Approach 2:
The patent implements feedback through voltage detection circuits that continuously monitor power domain stability. The isolation signals are generated based on real-time voltage status feedback, allowing the system to dynamically control level shifter enablement and disablement, ensuring operational stability while optimizing power-up time
2Loss of time
If level shifters are enabled early during power-up, then power-up time is reduced, but contention currents damage the chip
Solution Approach 1:
The patent applies preliminary action by performing voltage detection and stability verification before enabling level shifters. The system checks whether source and destination power domains are both stable before activating level shifters, preventing contention currents from damaging the chip while minimizing power-up time
Solution Approach 2:
The patent uses voltage detection circuits and isolation signal generation logic as intermediaries between power domains and level shifters. These intermediaries monitor power domain stability and control level shifter enablement timing, preventing direct contention current damage while maintaining efficient power-up sequencing
3Device complexity
If power domains are managed independently, then device complexity is reduced, but noise coupling among power domains increases
Solution Approach 1:
The patent merges independent power domain management into a unified PORS architecture that coordinates all power domains through centralized voltage detection and isolation signal generation. This consolidated approach maintains manageable device complexity while effectively preventing noise coupling among power domains through synchronized level shifter control
4Object-affected harmful factors
If isolation signals are delayed for PL power-down, then noise coupling to NoC block is reduced, but power-up time increases
Solution Approach 1:
The patent applies local quality by implementing selective delay of isolation signals based on specific power domain transitions. When PL power-down is detected, the isolation signal to NoC block is delayed locally to prevent noise coupling, while other power domain transitions proceed without delay, optimizing the balance between noise reduction and power-up time
Data Source
AI summary
Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power region. A level shifter circuit may be coupled to translate data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and logic gates may be configured to generate isolation signals between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC may be managed comprehensively during power-up to avoid unstable operation.