SoC Performance Profiling via Automated Test Code Instrumentation

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Solution Overview

Problem

Current methods for validating System on Chip (SoC) designs are time-consuming and labor-intensive, often lacking comprehensive coverage of use cases, and conventional debuggers are inadequate for debugging performance issues at runtime speeds.

Innovation Solution

A method and system for debugging SoCs that automatically generates test code with commands to print start and end times of actions, records these messages, and displays graphical representations of processing component activity over time, allowing for efficient identification of performance issues through a graphical user interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional debuggers are used for debugging performance issues, then debugging capability is provided, but debugging time is excessive and runtime speed is insufficient

Engineering Contradiction:
Improvedebugging timeVSAvoiddebugging efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent replaces conventional mechanical/debugger-based debugging methods with an automated software-based performance profiling system. The system automatically instruments test code, collects performance data, and generates visual profiles without manual intervention, substituting the mechanical debugger process with an automated software solution that operates at runtime speed.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The performance profiling system performs self-service by automatically generating test code with instrumentation, executing tests, collecting performance data, and generating visual profiles without requiring manual debugger operations. The system serves its own debugging function through automated end-to-end performance analysis.

Inventive Principle:
Principle #25Self-service

2Reliability

If basic directed bare-metal software tests are used for validation, then testing capability is provided, but test coverage is insufficient

Engineering Contradiction:
Improvetest coverageVSAvoidvalidation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The performance profiling system provides multi-functionality by combining test code generation, automated instrumentation, performance data collection, and visual profile generation into a single unified tool. This universal system handles multiple validation tasks that would otherwise require separate testing approaches, thereby improving test coverage without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces a performance profiling intermediary system that sits between the test code and the SoC under test. This intermediary automatically instruments the test code, captures performance metrics, and provides analysis, serving as a mediator that enhances test coverage without requiring direct complex validation efforts from the user.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If production software stacks are used for SoC validation, then software compatibility is maintained, but debugging capability is inadequate

Engineering Contradiction:
Improvevalidation accuracyVSAvoiddebugging ease
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent extracts performance profiling capability from the complex production software stack and conventional debugger environment. By separating the performance analysis function from the full software stack, the system provides accurate validation data without requiring the complexity of production software debugging, thereby improving debugging ease while maintaining validation accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10698805B1Method and system for profiling performance of a system on chip
Publication Date: 2020.06.30 CADENCE DESIGN SYST INC
  • US10698805B1 patent drawing
  • US10698805B1 patent drawing
  • US10698805B1 patent drawing

AI summary

A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.