SoC Queue Status Power Management

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Solution Overview

Problem

Existing power management systems in multi-processor SoCs are unable to make informed decisions about processor power usage based on actual workload, leading to inefficient energy consumption, especially in IO processing applications, and are not extensible to asymmetric or heterogeneous multiprocessor systems.

Innovation Solution

A power management controller monitors real-time queue levels and adjusts voltage and frequency dynamically based on pre-set thresholds, enabling or disabling processors as needed to match performance requirements, and can also manage memory and thermal conditions to optimize energy use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processors are kept in fully 'on' status to react to worst case loading conditions, then system reliability is improved, but energy consumption increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The power management controller proactively monitors queue depth and pre-empts processor activation by anticipating workload based on queue buildup patterns. This allows the system to activate processors before worst-case loading conditions occur, reducing the need to maintain all processors in fully 'on' status continuously, thus lowering energy consumption while preserving reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the power management controller continuously monitors actual queue depth and adjusts processor activation decisions based on real-time workload observations. This closed-loop control enables the system to respond to actual conditions rather than relying on conservative worst-case assumptions, optimizing the balance between reliability and energy consumption.

Inventive Principle:
Principle #23Feedback

2Device complexity

If software-based power management mechanisms are used, then device complexity is reduced, but measurement precision of actual workload decreases

Engineering Contradiction:
Improvedevice complexityVSAvoidworkload measurement precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The power management controller serves as an intermediary between the software driver and the actual hardware workload. It collects precise queue depth information from the hardware level and translates this into power management decisions, bridging the gap between simple software control and accurate workload measurement without requiring complex hardware modifications.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If a single host-to-SW driver manages power in symmetric multiprocessing, then ease of operation is improved, but adaptability to asymmetric or heterogeneous systems decreases

Engineering Contradiction:
Improveease of operationVSAvoidadaptability to asymmetric systems
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The power management controller is designed with universal functionality that works across symmetric and asymmetric multiprocessor configurations. It maintains a unified interface for power management while internally adapting to different system topologies and processor heterogeneities, making the same controller applicable to diverse system architectures without requiring configuration changes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of operation

If processors are enabled based on software observed workload, then ease of operation is improved, but productivity decreases due to reactive rather than proactive power management

Engineering Contradiction:
Improveease of operationVSAvoidproductivity
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The power management controller performs preliminary analysis of queue depth trends and workload patterns to proactively activate processors before they are actually needed. This predictive approach eliminates the reactive delay inherent in software-based systems, improving productivity by reducing latency in processor activation while maintaining ease of operation through automated decision-making.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8639862B2System-on-chip queue status power management
Publication Date: 2014.01.28 MACOM CONNECTIVITY SOLUTIONS LLC
  • US8639862B2 patent drawing
  • US8639862B2 patent drawing
  • US8639862B2 patent drawing

AI summary

A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.