SoC Rail Power Telemetry Using Averaged Voltage Sensing

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Solution Overview

Problem

Current rail power telemetry systems in SoCs face issues with bandwidth constraints and interface latencies in common-interface configurations, and increased costs and pin/logic requirements in dedicated-interface configurations, impacting power management efficiency and performance.

Innovation Solution

Implementing subsystems with output voltage sensing and averaging circuitry to calculate load current using a one-to-one arrangement with voltage regulators, eliminating the need for dedicated interfaces by calculating load current based on averaged output voltage and known relationships.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a common interface is used between PMIC and SoC for all voltage regulators, then the number of pins and logic is reduced, but interface bandwidth is constrained and latencies increase

Engineering Contradiction:
Improvenumber of pins and logicVSAvoidinterface latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments the interface architecture by providing dedicated interfaces for each voltage regulator subsystem rather than using a single common interface. This segmentation allows each subsystem to communicate independently with the PMIC, eliminating the bandwidth constraints and latency issues of shared interfaces while maintaining reasonable pin and logic complexity through systematic organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a universal interface architecture where each dedicated interface follows the same standardized protocol and structure. This universality allows the system to scale efficiently - each additional voltage regulator subsystem uses the same interface pattern, making the system multi-functional and adaptable without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of time

If dedicated interfaces are used for each voltage regulator, then interface latencies are reduced, but the number of pins and logic increases

Engineering Contradiction:
Improveinterface latencyVSAvoidnumber of pins and logic
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system divides the power management architecture into segmented independent interface channels, one for each voltage regulator. This segmentation provides dedicated communication paths that eliminate latency while the modular nature of the segmentation keeps pin and logic requirements manageable through systematic organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the interface architecture parameter from shared to dedicated, and simultaneously optimizes the protocol parameters to ensure that the increased number of interfaces does not proportionally increase complexity. The standardized protocol parameters allow for efficient scaling.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If periodic telemetry readings are transmitted over a common interface, then all subsystems can be monitored, but the interface bandwidth is constrained

Engineering Contradiction:
Improvesubsystem monitoring capabilityVSAvoidinterface bandwidth
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The telemetry monitoring system is segmented into dedicated interface channels for each subsystem. This allows each subsystem to transmit its telemetry data independently without competing for bandwidth, maintaining comprehensive monitoring capability while eliminating the bandwidth constraints of shared interfaces.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dedicated interfaces enable continuous, uninterrupted telemetry readings for each subsystem without the periodic interruptions and bandwidth contention that occur with shared interfaces. This continuity maintains monitoring versatility while maximizing effective bandwidth utilization.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250341550A1Systems and methods for performing rail power telemetry in a system-on-a-chip (SOC)
Publication Date: 2025.11.06 QUALCOMM INC
  • US20250341550A1 patent drawing
  • US20250341550A1 patent drawing
  • US20250341550A1 patent drawing

AI summary

Systems and methods are provided for performing rail power telemetry in an SoC by providing subsystems of the SoC with circuitry that senses an average of the respective output voltage delivered by a voltage regulator to the respective subsystem over a predetermined time period and uses the respective sensed average output voltage to calculate a load current on the respective load line.