SoC Read/Write Coordination for Strong and Relaxed Memory Ordering
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Solution Overview
Problem
Existing systems face challenges in ensuring that the sequence of globally observable execution results of read/write operations meets the requirements of both strong and relax order memory consistency models, leading to reduced transmission bandwidth and interaction efficiency between nodes with different memory consistency constraints.
Innovation Solution
A method and system on chip (SoC) that allows parallel execution of read/write operations by controlling the sequence of these operations through a first node that obtains permission from a third node, which complies with a relax order constraint, ensuring the sequence meets the requirements of a strong order constraint, thereby optimizing transmission bandwidth and interaction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential processing mechanisms are used to ensure execution sequence requirements of strong order model nodes, then execution sequence correctness is improved, but transmission bandwidth and interaction efficiency deteriorate
Solution Approach 1:
The patent introduces a first node as an intermediary between the second node (strong order model) and the third node (relax order model). This intermediary receives read/write requests from the second node, obtains operation permissions from the third node, and performs operations in parallel while ensuring the execution sequence meets the strong order model requirements. The intermediary enables parallel processing without compromising execution sequence correctness.
Solution Approach 2:
The patent segments the processing function into three distinct nodes with different responsibilities: the second node generates requests according to strong order constraints, the first node acts as an intermediary to manage permissions and coordinate operations, and the third node manages address permissions according to relax order constraints. This segmentation allows each node to operate independently and in parallel while maintaining overall sequence correctness through the intermediary's coordination.
2Productivity
If parallel processing of read/write operations is implemented, then transmission bandwidth and interaction efficiency are improved, but execution sequence control deteriorates
Solution Approach 1:
The first node performs preliminary actions by obtaining operation permissions from the third node before executing read/write operations in parallel. This preliminary permission acquisition ensures that even though operations are executed in parallel, the execution sequence can be controlled to meet the strong order model requirements. The permission management mechanism is established in advance to enable subsequent parallel processing.
Solution Approach 2:
The patent implements a feedback mechanism where the first node continuously monitors and coordinates the parallel operations to ensure they meet the execution sequence requirements of the strong order model. The intermediary node receives requests, manages permissions, and adjusts the execution sequence based on feedback from both the second node (request source) and the third node (permission manager), thereby maintaining sequence control during parallel processing.
Data Source
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AI summary
This application discloses a read/write operation execution method and a SoC chip, to implement that a sequence of globally observable execution results of performing a read/write operation by a node that complies with an RO constraint meets a requirement of a node that complies with an SO constraint. The read/write operation execution method includes: A first node receives a first message and a second message from a second node, where the first message is for requesting to perform a read/write operation on a first address managed by a third node, the second message is for requesting to perform a read/write operation on a second address managed by the third node, an execution sequence constraint of the read/write operation of the second node is stricter than an execution sequence constraint of the read/write operation of the third node; the first node obtains operation permission of the first address and operation permission of the second address from the third node; and the first node performs read/write operations on the first address and the second address.