SoC Replacement Mode Using Secondary Decoder
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Solution Overview
Problem
Semiconductor devices face challenges in switching out the controller (SoC) without losing data stored in volatile memory, as powering off the device to replace the SoC results in data loss, and existing solutions require additional pins or complex configurations to manage seamless transitions.
Innovation Solution
Implementing a system-on-chip (SoC) replacement mode that uses a secondary input circuit and decoder coupled to the command/address bus, allowing the memory to enter a self-refresh mode and ignore inputs except for replacement mode exit commands, utilizing existing pins for both entry and exit signals, and enabling seamless transitions between primary and backup SoCs without data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If the device is powered off to swap out the controller, then the controller can be replaced, but the information in the memory is lost
Solution Approach 1:
The memory device enters a self-refresh mode before the controller is removed, preserving data in advance. This preliminary action ensures that data remains intact during the controller replacement process, eliminating the need to power off the memory device and avoiding data loss.
Solution Approach 2:
A replacement mode entry signal acts as an intermediary between the controller and memory device, triggering the self-refresh mode. This signal mechanism enables seamless controller replacement while maintaining data integrity in the memory device.
2Reliability
If additional pins are added to manage seamless transitions, then controller replacement can be achieved without data loss, but device complexity increases
Solution Approach 1:
An existing pin (CA15) is assigned multiple functions: it serves as both a command/address bus line for normal operations and a replacement mode entry signal line. This multi-functionality enables controller replacement without data loss using existing infrastructure, avoiding the need for additional pins and reducing device complexity.
3Loss of information
If the memory enters self-refresh mode during replacement, then data integrity is maintained, but the memory cannot process normal commands during this period
Solution Approach 1:
The memory device dynamically switches between normal operation mode and self-refresh mode based on the replacement mode entry signal. This dynamic state transition allows the memory to preserve data during controller replacement while maintaining the ability to process commands normally after replacement is complete.
Data Source
AI summary
Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.