SOC Reset Sequence for Reduced Boot Time
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Solution Overview
Problem
Conventional integrated circuit devices have long boot times due to the SOC waiting for the main system processor to finish resetting, leading to increased user waiting time during the booting sequence.
Innovation Solution
The SOC is designed to reset simultaneously with the main system processor by using a chip controller that does not require a reference clock signal, a first chip element that does not operate with the reference clock, and a second chip element that operates with the reference clock, with the clock detector generating a notification signal to initiate resets based on a special ratio relationship between the reference and fixed clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SOC waits for the main system processor to finish resetting before starting to reset, then the reset sequence is simple and reliable, but the boot time becomes long
Solution Approach 1:
The SOC is divided into multiple chip elements (first chip element, second chip element, third chip element) that can be reset independently at different times. The chip controller manages staged resetting of these elements, allowing parallel reset operations while maintaining reliability through controlled sequencing.
Solution Approach 2:
The chip controller begins resetting chip elements before the main system processor finishes resetting. Specifically, the first chip element is reset during the main system processor's reset period, and the second chip element is reset after the main system processor finishes but before the third chip element, enabling overlapping reset operations that reduce total boot time.
2Loss of time
If the SOC resets simultaneously with the main system processor, then the boot time is shortened, but the reference clock signal frequency becomes unstable during reset
Solution Approach 1:
The first chip element that does not require the reference clock signal is reset preliminarily during the main system processor's reset period when the clock is unstable. This allows the SOC to start resetting early without being constrained by clock stability requirements.
Solution Approach 2:
The reset sequence is dynamically adjusted based on clock signal stability. The chip controller monitors the reset state of the main system processor and adapts the resetting timing of different chip elements accordingly, resetting clock-independent elements during unstable periods and clock-dependent elements after stability is achieved.
3Loss of time
If different chip elements are reset at different times, then the boot time is optimized, but the control logic becomes more complex
Solution Approach 1:
The control logic is segmented into distinct reset control paths for different chip elements. The chip controller uses separate control signals (first reset signal, second reset signal, third reset signal) for each chip element, with each signal generated based on simple, well-defined conditions related to the main system processor's reset state.
Solution Approach 2:
The chip controller acts as an intermediary that simplifies the overall control logic by centralizing the decision-making for reset timing. It monitors the main system processor's reset state and automatically generates appropriately timed reset signals for each chip element, abstracting away the complexity from the rest of the system.
Data Source
AI summary
A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.