SoC Reset Controller Isolating Processor State During PHY IP Block Reset
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Solution Overview
Problem
System-on-chip (SoC) devices often enter abnormal states such as deadlock, leading to inoperability and incorrect or missing data output to external devices, making it difficult to diagnose and reset without losing critical state information.
Innovation Solution
An SoC design with a reset controller that detects abnormal states and applies a reset signal to the PHY IP block, allowing it to output preset data to external devices during a reset period, while isolating the processor to preserve state information and allowing other components to be reset without affecting the processor's state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset signal is applied to the PHY IP block during abnormal state, then external devices can receive preset data and operate normally, but the processor state information may be lost
Solution Approach 1:
The system divides the reset operation into two independent parts: the processor and the PHY IP block. The reset controller can apply reset signals selectively to the PHY IP block without affecting the processor, allowing external devices to receive preset data while preserving processor state information for later diagnosis.
Solution Approach 2:
The reset controller acts as an intermediary between the processor and the PHY IP block. It monitors the processor state through a first bus and controls the PHY IP block through a second bus, enabling independent reset operations that prevent information loss while ensuring external device reliability.
2Stability of the object's composition
If the processor is reset during abnormal state, then system stability is restored, but critical state information is lost making diagnosis difficult
Solution Approach 1:
The reset controller performs preliminary monitoring of the processor state before applying any reset signals. By detecting abnormal states through the first bus and maintaining the ability to reset only the PHY IP block via the second bus, the system preserves processor state information that is critical for subsequent diagnosis and repair.
Solution Approach 2:
The system applies different reset strategies to different components based on their specific needs. The processor is protected from reset to preserve its state information, while the PHY IP block can be independently reset to restore system stability, allowing targeted recovery without losing diagnostic data.
3Reliability
If the PHY IP block is isolated from the processor during reset, then preset data can be output to external devices, but real-time data transfer is interrupted
Solution Approach 1:
The system dynamically adjusts the connection state between the processor and PHY IP block based on operational conditions. During normal operation, the first bus enables real-time data transfer for high productivity. During abnormal states, the reset controller can isolate the PHY IP block through the second bus to output preset data, temporarily sacrificing data transfer efficiency to ensure reliability.
Data Source
AI summary
A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.