SoC Reset Control Mechanism for Data Integrity and Voltage Stability
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Solution Overview
Problem
System on Chip (SoC) resets can cause data corruption and voltage spikes due to abrupt shutdowns, especially during normal operation, leading to incomplete data storage and potential system damage from voltage fluctuations.
Innovation Solution
A method for resetting the SoC that involves a controlled shutdown process, including completing atomic instructions, flushing write buffers, and gradually reducing clock signal rates to prevent data corruption and voltage spikes, using a dedicated reset pin or communication interface to manage the reset signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset signal is applied during normal operation to stop all processing actions, then the system can be set to a predefined condition, but data corruption occurs and voltage spikes are generated
Solution Approach 1:
The patent applies preliminary action by detecting the reset signal before it takes full effect and initiating a controlled shutdown sequence. The system identifies pending write operations and completes them or flushes them to non-volatile memory before the reset fully occurs, preventing data corruption. This early intervention allows the system to prepare for reset conditions while maintaining data integrity.
Solution Approach 2:
The patent implements skipping by rapidly completing or flushing pending write operations to non-volatile memory before the reset signal fully takes effect. The system rushes to finalize data writes that are at risk of corruption, using timeout mechanisms to ensure completion within the brief window before reset. This rapid action prevents data corruption while maintaining system reliability.
2Loss of information
If write operations are performed in memory during normal operation, then data is stored, but the data may be corrupted by reset events that stop processing during write actions
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a monitoring unit that detects reset signals and a controlled shutdown sequence that mediates between ongoing write operations and the impending reset. This intermediary system identifies pending writes and either completes them or flushes them to non-volatile memory, acting as a buffer that protects data integrity during the transition to reset state.
Solution Approach 2:
The system performs preliminary actions by detecting pending write operations before a reset event occurs and taking protective measures. The monitoring unit identifies in-progress writes and triggers completion or flush operations to non-volatile memory before the reset fully occurs, preventing corruption of volatile memory data while maintaining data integrity.
3Quantity of substance
If multiple simultaneous data writes are performed to different memories, then data storage capacity is increased, but data consistency and coherence across memories cannot be ensured during reset events
Solution Approach 1:
The patent implements feedback by introducing a monitoring unit that continuously observes ongoing write operations across multiple memory entities. When a reset signal is detected, the monitoring unit provides feedback about pending writes and coordinates their completion or flush operations. This feedback mechanism ensures that simultaneous writes to different memories are consistently handled, maintaining data coherence across all memory entities during reset events.
4Reliability
If a voltage regulator is used to power the SoC, then stable power supply is provided, but a sudden drop of electric load during reset causes voltage overshoot or spike that may cause malfunction or damage
Solution Approach 1:
The patent applies preliminary action by detecting the reset signal and initiating a controlled shutdown sequence that gradually reduces power consumption before the reset fully occurs. The system identifies components that can be powered down or have their clock signals reduced, and does so in advance of the reset event. This gradual reduction prevents sudden load drops that cause voltage spikes, while still allowing the reset to occur and set the system to a predefined condition.
Data Source
AI summary
A method for resetting a so-called System on Chip SoC is described as well as a system adapted and configured to perform the method. A reset signal applied to the SoC resets the system but at the same time prevents loss and corruption of data that was processed at the time of signal application.