SoC Reset Generation Using Early-Late Signals to Prevent Glitches
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Solution Overview
Problem
In System-On-a-Chip (SoC) designs, asynchronous resets can cause glitches that lead to issues such as inadvertent fuse burn, unsolvable board glitches, and incorrect PLL states, which are difficult to resolve through gate-level simulations and can result in catastrophic failures.
Innovation Solution
The implementation of a system and method that generates 'early' and 'late' versions of reset signals to manage race conditions, ensuring that critical components are reset correctly, thereby preventing glitches and ensuring the SoC operates correctly across various conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous reset signals are used in SoC designs, then reset functionality is provided, but glitches and race conditions occur causing catastrophic failures
Solution Approach 1:
The reset signal generation is segmented into multiple synchronized reset signals (first reset signal and second reset signal) that are generated at different times. This segmentation allows different components to be reset in a controlled sequence, preventing simultaneous state transitions that cause glitches and race conditions.
Solution Approach 2:
The first reset signal is generated before the second reset signal to preliminarily prepare critical components for resetting. This preliminary action ensures that components requiring earlier reset are properly initialized before other components are reset, preventing harmful race conditions.
2Ease of operation
If reset signals are generated simultaneously to all components, then reset is applied uniformly, but race conditions occur due to varying component readiness
Solution Approach 1:
The uniform reset application is segmented into multiple timed reset signals distributed to different components. Instead of a single simultaneous reset, the system generates multiple reset signals at different times based on component-specific requirements, eliminating race conditions while maintaining operational simplicity.
Solution Approach 2:
Different components receive reset signals with locally optimized timing characteristics. Critical components receive the first reset signal earlier, while other components receive the second reset signal later, allowing each component to be reset at the optimal moment for its specific readiness state.
3Difficulty of detecting and measuring
If gate-level simulations are used to detect reset issues, then detailed analysis is possible, but debugging time increases significantly
Solution Approach 1:
The system performs preliminary reset signal generation with built-in synchronization logic that prevents race conditions before they can occur. By embedding the solution at the system architecture level rather than requiring post-design simulation detection, debugging time is significantly reduced while maintaining comprehensive issue detection capability.
Data Source
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AI summary
Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.