SoC Reset Path Testing Through Functional Reset Synchronizers
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Solution Overview
Problem
Current SoC designs lack comprehensive test coverage for functional reset paths due to separate test and functional reset paths, limiting the effectiveness of reset tests on components and synchronizers.
Innovation Solution
A reset test system that allows a test reset to be transmitted through the same path as the functional reset path, utilizing a scan test controller and target reset controllers to synchronize and test each component and IP block during the reset test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test and functional reset paths are used, then the functional reset path can operate reliably during normal operation, but test coverage for functional reset paths is insufficient
Solution Approach 1:
The patent merges the separate test reset path and functional reset path into a unified reset path. The reset controller selectively outputs either a test reset signal or a functional reset signal through the same path, allowing the functional reset path to be used for both normal operation and testing, thereby achieving full test coverage without compromising operational reliability
Solution Approach 2:
The reset controller dynamically switches between test mode and functional mode based on operational requirements. During testing, the controller outputs test reset signals through the functional reset path; during normal operation, it outputs functional reset signals through the same path, enabling the system to adapt its behavior to different operational states
2Ease of manufacture
If a separate test reset path is used, then test reset can be applied to IP blocks, but synchronizers and components on the functional reset path cannot be tested
Solution Approach 1:
The functional reset path is designed to serve multiple functions: it operates as the normal functional reset path during regular system operation and as the test path during testing. The reset controller enables this multi-functionality by selectively generating and outputting appropriate reset signals through the same physical path, allowing all components including synchronizers to be tested comprehensively
3Measurement precision
If the functional reset path is used for testing, then comprehensive test coverage is achieved, but the reset control logic becomes more complex
Solution Approach 1:
The reset controller acts as an intermediary between the reset signal source and the destination components. It receives reset signals, determines whether the system is in test mode or functional mode based on control signals, and selectively outputs the appropriate reset signal through the functional reset path. This intermediary approach consolidates control logic in one component rather than requiring separate control mechanisms for test and functional paths
Data Source
AI summary
A reset test system and a system-on-chip, which enable a test reset to be transmitted through the same path as a functional reset in a reset test mode. The reset test system includes a scan test controller configured to generate a scan test enable signal, a scan reset control signal, and a scan reset deactivation signal; a target reset test controller configured to generate a target reset test mode signal and target reset test data; a leading target reset controller configured to synchronize a leading reset input to a functional clock in a functional mode and to output the target reset test data as a leading reset output in a scan test mode; and a following target reset controller configured to receive the leading reset output as a following reset input, synchronize it to the functional clock in the functional mode, and output the target reset test data.