SoC Reset Sequencing with Early and Late Asynchronous Resets
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Solution Overview
Problem
In System-On-a-Chip (SoC) designs, asynchronous resets can cause glitches that lead to issues such as inadvertent fuse burn, unsolvable glitches on I/O ports, and incorrect PLL states, which are difficult to resolve through gate-level simulations and can result in catastrophic failures.
Innovation Solution
The implementation of a system and method that generates 'early' and 'late' versions of reset signals to manage race conditions, ensuring that critical components are reset correctly, thereby preventing glitches and ensuring the integrity of SoC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous reset signals are used in SoC designs, then reset functionality is provided, but glitches and race conditions occur causing catastrophic failures
Solution Approach 1:
The patent applies preliminary action by generating an early reset signal before the normal reset signal. This early reset signal is used to preemptively reset critical components such as the fusebox and I/O pads before they are affected by the main reset signal, thereby preventing glitches and race conditions that would otherwise occur during asynchronous reset transitions.
Solution Approach 2:
The patent segments the reset signal into two distinct signals: an early reset signal and a normal reset signal. This segmentation allows different components of the SoC to be reset at different times, with critical components being reset first via the early signal, thereby eliminating the harmful race conditions that arise when all components are reset simultaneously or in incorrect sequence.
2Difficulty of detecting and measuring
If gate-level simulations are used to detect reset issues, then detection capability is provided, but debugging becomes excessively time-consuming
Solution Approach 1:
The patent incorporates reset issue prevention directly into the architectural design through the early reset signal mechanism, rather than relying on post-design detection methods. This preliminary action embeds the solution at the design stage, eliminating the need for extensive gate-level simulations and debugging, thereby dramatically reducing the time required to detect and resolve reset issues.
3Ease of manufacture
If ad-hoc adjustments are used to manage reset signals, then immediate fixes are provided, but root causes are not addressed
Solution Approach 1:
The patent addresses the root cause of reset signal management issues by implementing an architectural solution that generates an early reset signal specifically designed to preemptively reset critical components. This preliminary action eliminates the need for ad-hoc adjustments by providing a systematic, design-stage solution that prevents race conditions and glitches at their source, thereby ensuring both ease of manufacture and high reliability.
Solution Approach 2:
The patent segments the reset management function into distinct early and normal reset signal paths, allowing critical components to be handled differently from non-critical components. This segmentation provides a structured approach to reset signal management that addresses root causes rather than applying ad-hoc fixes, improving both manufacturability and signal integrity.
Data Source
AI summary
Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.