SoC Operational Robustness via Internal State Mimicry
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Solution Overview
Problem
Conventional methods for determining the operational robustness of System on a Chip (SoC) are inadequate, particularly in safety-critical systems, as they rely on slow simulations and invasive techniques like scan chain manipulation, which are not feasible or secure, and fail to accurately assess system behavior under real-world conditions.
Innovation Solution
A method and system that modifies internal states of the SoC during operation to mimic disturbances, generating signal traces to assess stability, using a bugger/stresser module with a disturbance injection unit, trace unit, and trigger/profile units to simulate transient and permanent failures, and analyze their effects on the SoC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If RTL simulation is used to model digital circuits, then diagnostic coverage can be demonstrated, but simulation speed becomes very slow and cannot be used for complex chips
Solution Approach 1:
The patent creates a simplified copy of the SoC architecture that replicates the essential behavior and failure modes needed for diagnostic coverage demonstration, but operates at a lower complexity level that enables fast simulation. This copy includes simplified models of critical components and their interconnections, allowing comprehensive fault injection and analysis without the computational burden of full RTL simulation.
2Measurement precision
If scan chain manipulation is used to test chip behavior, then internal states can be observed, but processing by the chip and surrounding systems must be temporarily suspended
Solution Approach 1:
The patent introduces an intermediary modeling layer that captures internal state behavior without requiring direct manipulation of the actual chip's scan chains. This intermediary model allows observation and analysis of internal states through simulated fault injection and trace generation, eliminating the need to suspend actual chip processing while maintaining the ability to assess robustness.
3Measurement precision
If scan chain read and write features are implemented, then internal states can be accessed, but severe security holes are created
Solution Approach 1:
The patent creates a secure copy of the SoC architecture that includes modeled internal states and fault injection capabilities. This copy provides the necessary accessibility for robustness assessment while isolating the actual chip from direct scan chain manipulation, thereby eliminating security vulnerabilities associated with implementing scan chain read/write features on the real device.
4Reliability
If redundant-type structures are integrated inside high integrity electronic systems, then error detection capability is improved, but power consumption and area increase
Solution Approach 1:
The patent applies partial redundancy by selectively placing redundant structures only in critical areas where error detection is most needed, rather than uniformly across the entire system. The modeling approach identifies critical components and their interconnections, allowing targeted implementation of redundancy that achieves high error detection capability with minimal impact on power consumption and area.
5Reliability
If redundant-type structures are integrated inside high integrity electronic systems, then error detection capability is improved, but area occupied increases
Solution Approach 1:
The patent implements partial redundancy by concentrating redundant structures in critical areas identified through the behavioral model, rather than distributing them uniformly throughout the chip. This targeted approach achieves high error detection capability for safety-critical functions while minimizing the overall area overhead.
Solution Approach 2:
The patent applies different redundancy strategies to different parts of the system based on their criticality. The behavioral model identifies which components and interconnections require higher levels of redundancy, allowing local optimization where robust error detection is essential, while accepting lower redundancy in non-critical areas to conserve chip area.
Data Source
AI summary
A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces.