System-on-a-chip ROM Error Correction for Manufacturing Yield

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Solution Overview

Problem

System-on-a-chip (SOC) manufacturing processes often face malfunctions or failures during the storage of chip information and security information in read-only memory (ROM), leading to incorrect or poor-quality data storage, which reduces manufacturing yield.

Innovation Solution

Incorporating error correction code (ECC) parity bits with the chip and security data stored in ROM, allowing for error detection and correction using an ECC decoder, ensuring accurate data retrieval and processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If chip information and security information are stored in ROM during manufacturing, then the SOC has permanent storage capability, but storage errors occur reducing manufacturing yield

Engineering Contradiction:

Improvestorage reliabilityVSAvoidmanufacturing yield

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-storing parity bits alongside the chip information and security information in the ROM during the manufacturing process. This preparatory measure enables error detection and correction to be performed later without requiring re-manufacturing, thus maintaining high manufacturing yield while ensuring storage reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses parity bits as an intermediary element that mediates between the stored data and the error detection/correction process. These parity bits act as a buffer or check mechanism that allows the system to verify and correct storage errors without compromising the integrity of the original chip information and security information.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If error correction is implemented using ECC parity bits, then data integrity is improved, but device complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidprocessing complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements partial error correction by using parity bits that can detect and correct a limited number of errors rather than attempting to handle all possible error scenarios. This approach achieves sufficient data integrity for manufacturing purposes while avoiding the excessive complexity of comprehensive error correction schemes.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8381073B2System-on-a-chip storing chip data and/or security data and method of processing chip data and/or security data for a device

Publication Date: 2013.02.19 SAMSUNG ELECTRONICS CO LTD

AI summary

A system-on-a-chip (SOC) includes a memory system, a data processor and a read only memory (ROM). The memory system includes random access memory and a memory controller. The data processor includes at least one functional block that communicates data with the memory system via the memory controller. The ROM stores data and one or more parity bits for detecting and correcting errors in the data. The data includes chip information and/or security information for the SOC. A method of using the SOC includes storing data in the ROM that includes chip information and/or security information for the SOC; storing in the ROM the one or more parity bits for the data; reading the data and the one or more parity bits from the ROM; detecting and correcting errors in the data using the one or more parity bits; and outputting the corrected data.