SOC Voltage and Frequency Scaling Under Thermal Resistance Limits
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Solution Overview
Problem
Mobile device microprocessors face thermal constraints due to passive cooling, leading to performance limitations as existing techniques lack a systematic method to characterize and manage thermal limits effectively, particularly in determining optimal voltage and frequency scaling.
Innovation Solution
A performance setting technique that utilizes total thermal resistance to determine the maximum power consumption of a System-on-a-Chip (SOC) without exceeding its thermal limit, allowing for intelligent selection of voltage and frequency settings to maximize performance while adhering to thermal constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SOC operates at high performance settings, then processing power increases, but thermal limit is exceeded
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling (DVFS) that continuously adjusts the SOC operating parameters based on real-time thermal conditions. The system transitions from static performance settings to dynamic adaptation, where voltage and frequency are adjusted in response to thermal feedback, enabling the processor to operate at high performance when thermal conditions permit while automatically reducing power consumption when approaching thermal limits.
Solution Approach 2:
The patent changes the operating parameters (voltage and frequency) of the SOC based on thermal resistance measurements and thermal limit calculations. By systematically varying these parameters according to thermal conditions rather than using fixed settings, the system optimizes the balance between processing power and thermal management, resolving the contradiction between high productivity and temperature control.
2Ease of manufacture
If ad hoc techniques are used to determine maximum performance setting, then implementation is simple, but determination accuracy is poor
Solution Approach 1:
The patent replaces ad hoc trial-and-error methods with a systematic thermal model-based approach. Instead of relying on empirical testing and manual adjustment, the system uses thermal resistance calculations and thermal limit modeling to determine optimal performance settings. This substitution of systematic calculation for empirical methods improves measurement precision while maintaining implementation feasibility through automated algorithms.
Solution Approach 2:
The patent implements a feedback mechanism where thermal performance data is continuously monitored and used to adjust performance settings. The system measures actual thermal behavior, compares it against thermal limits, and automatically adjusts voltage and frequency accordingly. This closed-loop feedback replaces open-loop ad hoc techniques, providing accurate performance characterization through iterative optimization based on thermal feedback.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the SOC to operate at its maximum performance without exceeding thermal limits, providing a systematic and efficient method for determining optimal power consumption and performance settings, unlike ad hoc methods that rely on trial and error.
Implementation Method 1
The disclosed performance setting technique exploits the total thermal resistance to determine what amount of power an SOC can consume without exceeding its thermal limit
Data Source
AI summary
A performance setting technique is disclosed for a clocked circuit such as a processor in an integrated circuit. The technique determines a maximum power consumption for the clocked circuit as a function of a total thermal resistance of a mobile device incorporating the integrated circuit. The total thermal resistance is a sum of a system thermal resistance for the mobile device and a device thermal resistance for the integrated circuit.


