Scan Bypass for SoC Yield Loss Reduction
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Solution Overview
Problem
Current scan testing and memory built-in self-test (BIST) methods for integrated circuits result in unintentional yield loss and excessive power consumption by testing all IP blocks, including those that are masked out or non-functional in specific package types, leading to unnecessary time and cost.
Innovation Solution
A system and method that uses chip package information to automatically bypass scan chains and BIST controllers for non-common IP blocks, employing bypass-signal generators and clock gating circuits to prevent testing of unused blocks, thereby reducing yield loss and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full scan and full memory BIST tests are performed on all IP blocks, then all faults are detected, but unintentional yield loss occurs due to testing masked-out blocks
Solution Approach 1:
The patent segments the test process by dividing IP blocks into common blocks (tested) and non-common blocks (bypassed). The bypass-signal generator creates separate test paths based on package type, allowing selective testing of only relevant IP blocks. This segmentation resolves the contradiction by maintaining comprehensive fault detection for functional blocks while avoiding unnecessary testing of masked-out blocks that causes yield loss.
Solution Approach 2:
The patent applies local quality by making the test coverage different for different regions of the IC based on package type. Common IP blocks receive full testing coverage, while non-common IP blocks receive bypassed testing. This localized differentiation ensures reliable fault detection where needed while improving yield by avoiding testing of irrelevant blocks in specific package configurations.
2Reliability
If full scan and full memory BIST tests are performed on all IP blocks, then complete testing is achieved, but excessive power consumption occurs
Solution Approach 1:
The patent segments the testing process into two distinct paths: one for common IP blocks that requires full testing, and another for non-common IP blocks that uses bypass signals. This segmentation enables complete testing of functional blocks while avoiding the excessive power consumption associated with testing all blocks including masked-out ones.
Solution Approach 2:
The patent applies partial action by performing testing only on the necessary portion of IP blocks rather than all blocks. The bypass-signal generator enables selective testing of common blocks while bypassing non-common blocks, thereby achieving adequate testing coverage without the excessive power consumption of full testing.
3Reliability
If full scan and full memory BIST tests are performed on all IP blocks, then all faults are detected, but unnecessary time is consumed
Solution Approach 1:
The patent segments the test execution time by processing common IP blocks sequentially through full testing while bypassing non-common IP blocks. The bypass-signal generator manages test time efficiently by parallelizing the testing of common blocks while skipping non-common blocks, thereby reducing total test time without compromising fault detection coverage for functional blocks.
Solution Approach 2:
The patent applies partial action by performing testing only on necessary IP blocks rather than all blocks. This selective testing approach achieves adequate fault detection coverage for common blocks while significantly reducing the unnecessary time consumption associated with testing all blocks including masked-out ones.
Data Source
AI summary
A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.