SOC Scan Chain Trigger Signal Delay Control
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Solution Overview
Problem
The dynamic voltage drop during scan testing of system on chip (SOC) can lead to a drop in test reliability, particularly when testing logic circuits and asynchronous set/reset signals, as multiple logic circuits change simultaneously, affecting the accuracy of the test results.
Innovation Solution
A system on chip (SOC) that includes a delay controller and a delay signal generating unit to control the delay of trigger signals, such as clock or set/reset signals, within scan chains, allowing for selective delay of these signals to prevent simultaneous changes in logic circuits, thereby maintaining test reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a scan test method is used to test logic circuits in SOC, then test coverage is improved, but dynamic voltage drop causes test reliability to deteriorate
Solution Approach 1:
The trigger signal input to multiple scan chains is segmented into different delay paths. Each scan chain receives the trigger signal at a different time through dedicated delay circuits, dividing the simultaneous switching event into sequential events. This segmentation reduces the number of circuits switching at any given moment, thereby reducing dynamic voltage drop and improving test reliability.
Solution Approach 2:
Delay values for each scan chain are predetermined and configured before the test operation begins. The delay controller is pre-programmed with specific delay values for each scan chain based on their positions and characteristics, allowing the system to proactively compensate for voltage drop issues before they occur during testing.
2Productivity
If multiple scan chains operate simultaneously with the same trigger signal, then testing efficiency is improved, but simultaneous logic circuit changes cause dynamic voltage drop that reduces test accuracy
Solution Approach 1:
The system dynamically adjusts the timing of trigger signals for different scan chains by introducing variable delays. While all scan chains still operate in parallel (maintaining efficiency), their trigger signals are staggered in time through dynamic delay control, preventing simultaneous switching and reducing voltage drop that would compromise test accuracy.
3Reliability
If asynchronous set/reset signals are used to test error paths, then error detection capability is improved, but output changes from multiple flip-flops cause dynamic voltage drop that reduces test reliability
Solution Approach 1:
The application of asynchronous set/reset signals to multiple flip-flops is segmented into sequential operations. Each flip-flop or group of flip-flops receives the reset signal at different times through individually controlled delay circuits, preventing simultaneous state changes that would cause dynamic voltage drop and ensure reliable error path testing.
Data Source
AI summary
A system on chip (SOC) is provided. The system on chip (SOC) includes: at least one core including a plurality of scan chains operated by a trigger signal; a delay controller generating a delay target selection signal selecting at least one of the plurality of scan chains and a delay depth control signal indicating a delay depth of the trigger signal; and a delay signal generating unit delaying the trigger signal based on the delay target selection signal and the delay depth control signal and providing the delayed trigger signal to the plurality of scan chains.