SoC Scan Register Inverting Circuit for AT-Speed Test
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Solution Overview
Problem
Existing system-on-chip (SoC) technologies face challenges in efficiently performing AT-SPEED tests on interface circuits between multiple cores, as individual core testing methods do not effectively identify transition delay faults in these interfaces.
Innovation Solution
The implementation of a system-on-chip with a first and second scan register, an inverting circuit on the feedback path, and a logic circuit on the data path between the registers, which generates and processes test data to identify transition delay faults during the AT-SPEED test, allowing for efficient testing regardless of core positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual core testing is performed, then testing simplicity is maintained, but transition delay faults in interface circuits cannot be properly identified
Solution Approach 1:
The patent merges multiple scan registers (first scan register, second scan register, and third scan register) into a unified test configuration that spans across multiple cores. This combination enables the test system to capture and analyze transition delay faults in interface circuits between cores, which cannot be detected when testing cores individually. The merged register structure allows simultaneous observation of data transitions across core boundaries.
2Reliability
If AT-SPEED test is performed on interface circuits, then transition delay faults can be identified, but test configuration becomes complex
Solution Approach 1:
The patent segments the test configuration into distinct functional components: a first scan register for capturing initial data, a second scan register for holding expected results, and a third scan register for capturing actual results. This segmentation allows each component to perform its specific function efficiently while collectively enabling comprehensive interface circuit testing. The segmented approach makes the complex test configuration more manageable and implementable.
Solution Approach 2:
The patent introduces scan registers as intermediary elements between the test stimulus source and the interface circuits under test. These intermediary registers buffer and control the flow of test data, allowing precise timing control and facilitating the capture of transition delay faults without requiring direct complex connections between test equipment and interface circuits.
3Measurement precision
If two scan registers are used for AT-SPEED test, then transition delay faults can be detected, but device structure becomes more complex
Solution Approach 1:
The patent designs scan registers with multi-functionality, allowing them to serve multiple purposes: capturing test stimulus, holding expected result patterns, capturing actual output data, and providing timing control signals. By making the register structure universal and multi-functional, the patent reduces the need for separate dedicated components, thereby mitigating the increase in device complexity while maintaining high measurement precision for transition delay fault detection.
Data Source
AI summary
A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.