SoC Verification Scenario Models Thread Memory Scheduling
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Solution Overview
Problem
The verification of system-on-a-chip (SoC) designs is time-consuming and costly due to the need for multiple efforts and tools, with random input stimuli often failing to exercise all functions, leading to bugs being discovered late in the development process and increasing time-to-market risks.
Innovation Solution
The development of portable scenario models that test various combinations of SoC functions, allowing for the generation of stimulus and comparison with expected outcomes to determine operational status, and the use of these models across different project stages with optimized memory and thread scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional simulation acceleration, emulation and/or FPGA prototype are used to verify SoC designs, then verification capability is improved, but time consumption and cost increase significantly
Solution Approach 1:
The patent creates virtual copies of hardware blocks through scenario models that can be executed on standard processors. These scenario models replicate the behavior of actual hardware blocks without requiring physical hardware, allowing verification to proceed using software-based simulation that is both reliable and time-efficient.
Solution Approach 2:
The patent replaces complex mechanical verification systems (emulation hardware, FPGA prototypes) with software-based scenario models that run on standard processors. This substitution eliminates the need for specialized hardware while maintaining verification capability, significantly reducing time consumption and cost.
2Ease of manufacture
If random input stimulus is used for verification, then test generation is simplified, but coverage of all functions is insufficient
Solution Approach 1:
The patent performs preliminary analysis of the hardware block's functionality and pre-generates scenario models that cover all expected operational paths. By preparing these scenario models in advance based on formal specifications, the system ensures comprehensive function coverage while maintaining the simplicity of automated test generation.
Solution Approach 2:
The patent implements a feedback mechanism where scenario models are continuously refined based on verification results and coverage analysis. The system monitors which functions are exercised and automatically adjusts scenario generation to ensure complete coverage, transforming the simple random stimulus approach into a directed, comprehensive testing strategy.
3Adaptability or versatility
If verification is performed at later stages of SoC development, then design flexibility is maintained, but bug detection capability is reduced
Solution Approach 1:
The patent enables verification activities to be performed early in the design process by creating scenario models from formal specifications before hardware implementation. This preliminary verification maintains design flexibility while detecting bugs early, as the scenario models can be executed and validated independently of the physical hardware.
Solution Approach 2:
The patent segments the verification process into independent scenario models that can be developed and executed separately from the full SoC design. This segmentation allows verification to proceed in parallel with design development, maintaining flexibility while improving bug detection capability through iterative testing of individual functional blocks.
Data Source
AI summary
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.