SoC Scheduler Hardware Arbitration for Real-Time Shared Interface
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Solution Overview
Problem
Existing methods for scheduling a system-on-chip (SoC) with a real-time shared interface require many software resources and increase system complexity, making it difficult to guarantee critical time boundaries (CTBs) for multiple central processing units (CPUs) sharing a slave device.
Innovation Solution
A scheduling method that involves a scheduler setting and managing time limit values for access requests from multiple masters, determining if the system satisfies operational preconditions, selecting the access request with the minimum time limit value, and adjusting these values to ensure real-time operation, using a shared interface like I2C, UART, or SPI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If scheduling is performed using software according to the related art, then the system can operate multiple application programs, but the system requires many soft resources and the complexity of the system increases
Solution Approach 1:
The patent introduces a dedicated hardware scheduler as an intermediary component between multiple masters and the shared slave device. This scheduler includes registers for storing access requests, counters for tracking time limits, and logic for automatic arbitration. By offloading the scheduling function to this specialized hardware mediator, the system achieves real-time scheduling capability without requiring complex software resource management, thus resolving the contradiction between versatility and system complexity
2Reliability
If a slave is controlled using one real-time shared interface, then the system can be operated in real time by guaranteeing CTB, but it becomes difficult to manage multiple masters sharing the interface
Solution Approach 1:
The patent segments the interface management function by providing separate registers and time limit counters for each master device. Each master has its own dedicated register for storing access requests and its own counter for tracking the time limit. This segmentation allows the system to manage multiple masters independently while maintaining real-time guarantees for each, resolving the contradiction between reliability and management complexity
3Adaptability or versatility
If multiple masters share a slave device, then the system can handle multiple access requests, but the critical time boundary may not be guaranteed without proper scheduling
Solution Approach 1:
The patent implements preliminary action by pre-allocating dedicated registers and time limit counters for each master before access requests are generated. When access requests are received, the scheduler immediately compares the time limit values stored in the counters and selects the request with the minimum time limit. This pre-established structure enables immediate real-time scheduling decision-making, ensuring critical time boundaries are guaranteed while handling multiple access requests simultaneously
Data Source
AI summary
A method of scheduling a system-on-chip (SoC) by a scheduler, located between a plurality of masters and a slave, includes receiving a plurality of access requests from the plurality of masters, setting the plurality of access requests in a plurality of registers, and scheduling the plurality of access requests based on the plurality of access requests.