SOC Design Abstraction via Signal Grouping and Bucket Sorting
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Solution Overview
Problem
Complex System-on-Chip (SOC) designs are difficult to understand and modify due to their large size and poor documentation, often existing only at a low register transfer level (RTL) description, making it challenging for design teams to reuse and modify them without access to original designers.
Innovation Solution
A method is introduced to generate a higher-level description of SOC designs by grouping related signals, creating abstracted descriptions with lower complexity, using bucket sorting, interface instance generation, and rule-based analysis to establish pin-pin connectivity and signal groupings, allowing for easier understanding and modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a detailed low-level RTL description is used to accurately represent the circuit design, then the design information completeness is improved, but the design complexity and difficulty to understand increases
Solution Approach 1:
The patent segments the detailed RTL signal netlist into hierarchical groups organized by functional modules. Individual signals are clustered into signal groups that represent functional units, which are further organized into modules. This segmentation reduces the perceived complexity by presenting information in manageable hierarchical layers rather than as a flat overwhelming list of individual signals.
Solution Approach 2:
The patent introduces a hierarchical dimension to the design representation. Instead of presenting signals in a single flat level, it creates multiple abstraction levels (individual signals → signal groups → functional modules). This dimensional transformation allows designers to navigate from detailed views to abstracted views, maintaining information completeness while reducing complexity at any given viewing level.
2Measurement precision
If individual signal names are listed to provide detailed design information, then the design accuracy is improved, but the ease of understanding deteriorates due to overwhelming complexity
Solution Approach 1:
The patent merges individual signal names into grouped representations that preserve connectivity information. Signals that are functionally related are combined into signal groups with representative names, maintaining the accuracy of signal relationships while reducing the number of individual names that must be processed and understood. The merging maintains precision through preserved connectivity data.
Solution Approach 2:
The patent applies different levels of detail to different parts of the design representation. Highly connected or critical signals may be represented with more detail, while less critical signals are grouped more abstractly. This local quality approach allows the representation to adapt its level of detail to the functional importance of different signal groups, improving overall understandability while maintaining necessary accuracy.
3Reliability
If the original detailed design documentation is retained to ensure design fidelity, then the design reliability is improved, but the ease of modification and reuse deteriorates due to complexity
Solution Approach 1:
The patent performs preliminary organization of the detailed design data into hierarchical structures before the design needs to be modified or reused. By pre-grouping signals into functional modules and establishing the hierarchical organization in advance, the system prepares the design information in a form that is both faithful to the original design and ready for efficient modification. This preliminary structuring reduces the effort required for future design changes.
Solution Approach 2:
The hierarchical module structure created by the patent serves multiple functions: it preserves design fidelity for analysis, enables easy modification by allowing selective editing of modules, and facilitates reuse by allowing modules to be extracted and applied to other designs. This multi-functional structure simultaneously supports reliability, modifiability, and reusability.
Data Source
AI summary
Provided are systems and methods for generating a higher level description of a circuit design comprising a plurality of interface instances. One or more buckets for each source instance with respect to each destination instance included in the circuit design are generated, and then the one or more buckets are sorted based on a number of bucket entries in each bucket. One or more interface instances are generated based on the sorted buckets. The higher level description of the circuit design is generated based on the one or more interface instances.