SoC State Reporting via Reset-Persistent Registers
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Solution Overview
Problem
Current processor architectures lack efficient mechanisms for customizable and detailed reporting of hardware errors, limiting the ability to effectively debug and profile hardware behavior, especially in secure environments where high-level system failure information is insufficient.
Innovation Solution
Implementing a system where circuit subsystems of a processor or SoC can pause and store signal states in reset-persistent registers, select subsets of these states based on configurations, and propagate hardware error signals to other subsystems, allowing for customizable and detailed error reporting without requiring hardware unlocking or JTAG-based methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional MCA error reporting mechanisms are used, then hardware errors can be reported in architecturally defined registers, but the error data is lost after reboot requiring system reinitialization
Solution Approach 1:
The patent applies preliminary action by capturing and storing error state data in persistent storage media before the system reboot occurs. The error data is saved to a storage location that survives reboot, allowing debugging information to be preserved and analyzed after the system restarts without requiring reinitialization or loss of critical error state information.
2Measurement precision
If detailed processor state data is collected for debugging, then hardware behavior can be profiled in-depth, but security may be compromised in secure environments
Solution Approach 1:
The patent applies segmentation by dividing the error reporting mechanism into separate functional components: error detection logic, state capture mechanisms, and persistent storage. This segmentation allows detailed error state data to be captured and stored without requiring system-wide security compromises, as the data collection is isolated to specific error handling pathways rather than requiring full system access.
Solution Approach 2:
The patent introduces an intermediary mechanism that captures error state data through dedicated error handling pathways rather than requiring direct access to protected system resources. This intermediary approach allows detailed error information to be obtained while maintaining security boundaries, as the data is captured through controlled error reporting interfaces rather than breaking security models.
3Reliability
If hardware error signals are propagated through multiple subsystems, then comprehensive error coverage is achieved, but the complexity of error handling increases
Solution Approach 1:
The patent applies universality by implementing a standardized error signal propagation mechanism that can be uniformly applied across multiple subsystems. The same error capture and storage logic is reused in each subsystem, providing comprehensive error coverage without requiring custom complex handling for each individual subsystem. This multi-functional approach simplifies the overall error handling architecture.
Data Source
AI summary
The disclosed computer-implemented method includes receiving, by a first circuit subsystem, a hardware error signal and storing, in response to the hardware error signal, a signal state of the first circuit subsystem in a reset-persistent register. The method also includes sending, by the first circuit subsystem, the hardware error signal to a second circuit subsystem. Various other methods, systems, and computer-readable media are also disclosed.