Static Page Buffering in SoC Address Translation
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Solution Overview
Problem
Existing system-on-chips (SoCs) face challenges in efficiently managing limited memory resources to rapidly execute multiple application programs, necessitating improved access speed for virtual to physical address translations.
Innovation Solution
Incorporation of a translation lookaside buffer (TLB) and a static page management (SPM) circuit within the SoC, which includes a static page management buffer (SPMB) to store frequently accessed address translation information, allowing parallel search and prioritization of static pages, thereby optimizing address translation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a TLB stores both static and dynamic address translation information, then the system can handle multiple types of pages, but the access speed for static pages deteriorates due to unnecessary searches
Solution Approach 1:
The patent segments the address translation information storage into two separate buffers: a TLB for dynamic pages and an SPMB for static pages. This segmentation allows each buffer to be optimized for its specific purpose, with the SPMB storing only static page translations that require fast access, while the TLB handles dynamic translations. By separating the storage functions, the system eliminates unnecessary searches in the TLB for static pages, thereby improving access speed while maintaining the ability to handle both page types.
Solution Approach 2:
The patent extracts static page address translation information from the general TLB and places it in a dedicated SPMB. This extraction removes the harmful element (unnecessary searches in TLB for static pages) while preserving the useful function (fast access to static page translations). The SPMB is specifically designed to store only static page information, allowing the system to take out the static page handling function from the mixed TLB and optimize it separately.
2Reliability
If the system performs sequential searches in TLB and page table, then comprehensive address translation can be achieved, but the time consumption increases
Solution Approach 1:
The patent implements preliminary action by pre-storing static page address translation information in the SPMB before it is needed. When a static page access occurs, the system can directly query the SPMB without performing a full page table walk, thereby reducing time consumption while maintaining translation completeness. The SPMB acts as a pre-computed cache for static pages, allowing fast retrieval without sequential searching.
Solution Approach 2:
The patent adds another dimension to the address translation hierarchy by introducing the SPMB as a separate storage layer for static pages. Instead of a single sequential search path (TLB → page table), the system now has a dual-path approach: direct SPMB access for static pages and TLB/page table path for dynamic pages. This dimensional expansion allows parallel processing of different page types and eliminates the time-consuming sequential search for static pages.
3Adaptability or versatility
If the TLB is searched for every address translation request, then all page types can be served, but the productivity decreases due to redundant searches
Solution Approach 1:
The patent applies local quality by tailoring the search strategy to the specific type of page being accessed. For static pages, the system uses a dedicated SPMB with optimized fast access, while for dynamic pages, it uses the TLB with standard search procedures. This localized optimization ensures that each page type receives the appropriate handling mechanism, improving overall productivity by avoiding redundant TLB searches for static pages while maintaining support for both page types through differentiated access paths.
Data Source
AI summary
A system-on-chip includes a translation lookaside buffer (TLB) that stores a portion of address translation information for translating between virtual addresses and physical addresses, a core that executes an instruction and accesses the TLB, a page table walker that performs a page table walk operation of searching a page table that stores the address translation information, and a static page management (SPM) circuit that, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stops access to the TLB by the core or stops the page table walk operation.