Asymmetric SoC Package Substrate Stackup for Higher Output
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Solution Overview
Problem
Current system-on-chip (SoC) package substrates have a symmetric stackup structure that results in unnecessary material costs and reduced production efficiency, as many backside layers contribute no technological benefit despite being required by manufacturing equipment design.
Innovation Solution
An asymmetric stackup structure is introduced for SoC package substrates, featuring a substrate core with recesses for integrated passive devices and build-up layers only on the top core, reducing material usage and allowing for increased production output without requiring significant capital investment in new equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a symmetric stackup structure is used for SoC package substrates, then manufacturing equipment compatibility is maintained, but material costs increase and production efficiency decreases
Solution Approach 1:
The patent applies asymmetry by designing a substrate structure where build-up layers are present only on the front side of the substrate core, while the back side remains without build-up layers. This asymmetric configuration eliminates unnecessary materials while maintaining compatibility with existing symmetric manufacturing equipment through process adaptation.
Solution Approach 2:
The patent extracts and removes the backside build-up layers from the traditional symmetric substrate structure. By taking out only the necessary front-side build-up layers and eliminating redundant back-side layers, the design reduces material costs while preserving essential functionality.
2Ease of manufacture
If a symmetric stackup structure is used for SoC package substrates, then equipment design requirements are met, but production efficiency is reduced
Solution Approach 1:
The asymmetric substrate structure enables higher production efficiency by reducing the number of layers that need to be manufactured and processed. The simplified structure allows for faster fabrication cycles while existing equipment can accommodate the asymmetric design through process parameter adjustments.
Solution Approach 2:
The patent applies partial action by implementing build-up layers only where necessary (front side) rather than uniformly on both sides. This partial implementation reduces manufacturing complexity and increases production speed without compromising functional requirements.
3Ease of manufacture
If build-up layers are formed on both sides of the substrate core, then symmetric manufacturing process is maintained, but material usage increases
Solution Approach 1:
The patent implements asymmetry by forming build-up layers exclusively on the front side of the substrate core, eliminating back-side build-up layers. This reduces material usage significantly while the symmetric manufacturing equipment can still be used with modified processing sequences.
Solution Approach 2:
The patent applies local quality by concentrating build-up layers only in the front-side region where they are functionally necessary. This localized approach optimizes material distribution, placing materials only where needed rather than uniformly across the entire substrate.
4Ease of manufacture
If traditional symmetric substrate structure is used, then manufacturing consistency is maintained, but production output is limited
Solution Approach 1:
The patent segments the substrate manufacturing process into distinct front-side and back-side operations. The asymmetric structure allows independent processing of each side, enabling parallel manufacturing workflows that increase overall production output while maintaining consistency through standardized process modules.
Solution Approach 2:
By implementing partial build-up layers only on the front side, the patent reduces manufacturing cycle time and enables faster production turnover. The simplified structure requires fewer processing steps while existing equipment maintains manufacturing consistency through established process controls.
Data Source
AI summary
An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.