SoC Internal to External Memory Data Transmission via Task Queue
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In system-on-chip (SoC) data transmission, the processor often wastes resources due to improper timing in initiating data transfer tasks with a Direct Memory Access (DMA) device, leading to waiting periods and reduced efficiency in data transfer between internal and external memories.
Innovation Solution
A data transmission method utilizing a task queue to manage execution information for DMA tasks, allowing the processor to send tasks sequentially to the DMA device, reducing waiting times and improving resource utilization by maintaining continuous processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor initiates data transmission tasks with the DMA device in real-time, then the processor can execute other computing tasks during transmission, but the DMA device remains idle when no tasks are available, causing processor waiting time and resource waste
Solution Approach 1:
The processor pre-generates and queues multiple data transmission tasks in advance before the DMA device completes previous tasks. This ensures that when the DMA device finishes one task, there are already subsequent tasks ready to execute, eliminating idle time and processor waiting periods.
Solution Approach 2:
By maintaining a task queue with pre-generated transmission tasks, the system ensures continuous operation of the DMA device without idle periods. The processor can continuously fetch and submit new tasks from the queue, keeping the data transmission pipeline full and eliminating gaps in useful action.
2Ease of operation
If the processor waits for DMA task completion before initiating the next task, then task execution is sequential and simple to manage, but the processor cannot execute other computing tasks during transmission, wasting computing resources
Solution Approach 1:
The data transmission workflow is segmented into independent tasks that are queued and processed sequentially by the DMA device. Each task is self-contained with specific source and destination addresses, allowing the processor to manage tasks through simple queue operations while the DMA handles execution independently, improving both simplicity and processor utilization.
3Adaptability or versatility
If the DMA device operates with idle periods between tasks, then the system can manage task timing more flexibly, but the transmission interval increases, reducing overall data transmission throughput
Solution Approach 1:
Multiple data transmission tasks are generated and queued in advance before the DMA device completes previous operations. This preliminary preparation ensures that when the DMA device becomes available, tasks are already ready to execute immediately, maintaining high throughput while preserving timing flexibility through the queue structure.
Data Source
AI summary
A data transmission method and device for data transmission between an internal memory of a system-on-chip and an external memory coupled to the system-on-chip. The method is executed by a processor of the system-on-chip, including steps of: adding execution information of at least one data transmission task to be executed to a task queue; sending execution information of one data transmission task in the task queue to a direct access device for the direct access device to execute the data transmission task; and receiving an interrupt request sent by the direct access device, where the interrupt request is used to indicate completion of the execution of the data transmission task, so that the processor sends execution information of a next data transmission task to be executed in the task queue to the direct access device.