SoC Test Bus Allocation Through Data Distribution Circuits
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Solution Overview
Problem
Current test solutions for system-on-chip (SoC) face challenges such as winding congestion and complex configuration processes, leading to high test costs and low efficiency, particularly with increasing numbers of circuit modules and limited chip pins.
Innovation Solution
A test circuit and method that utilizes a data distribution circuit with selectors and registers to dynamically allocate test buses, enabling efficient data transmission and reducing congestion, while configuring circuits to sleep mode to conserve power and simplify the configuration process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a small quantity of chip pins are multiplexed using a multiplexer to test a larger quantity of test scan channels, then the number of test scan channels increases, but winding congestion becomes severe and test costs increase
Solution Approach 1:
The chip is divided into multiple test domains, each with its own dedicated test bus. This segmentation allows multiple circuits to be tested simultaneously in parallel, eliminating the need for complex multiplexing and reducing winding congestion while increasing the number of testable scan channels.
Solution Approach 2:
The patent transitions from a single-dimension sequential test approach (one test bus serving all circuits) to a multi-dimensional parallel test approach (multiple test buses operating simultaneously). This dimensional expansion allows more circuits to be tested at the same time without increasing pin count, thereby reducing congestion.
2Ease of operation
If test scan data is transmitted by using a bus with complex hardware circuit for data exchange between bus and test compression logic, then data transmission is enabled, but hardware circuit scale increases and configuration process becomes complex
Solution Approach 1:
The test compression logic is extracted from the main test bus interface and integrated directly into each test domain. This eliminates the need for complex data exchange hardware between the bus and compression logic, simplifying the overall circuit architecture while maintaining data transmission capability.
Solution Approach 2:
The patent introduces a simplified interface mechanism that acts as an intermediary between the test bus and test domains. This intermediary handles data exchange in a standardized, simple manner, avoiding the need for complex dedicated hardware circuits for each connection.
3Adaptability or versatility
If a complex hardware circuit is configured for data exchange in various aspects, then data transmission functionality is achieved, but configuration process becomes complex and test efficiency decreases
Solution Approach 1:
The test bus interface is designed with universal, standardized connections that can serve multiple test domains simultaneously. This multi-functional design eliminates the need for separate complex configuration for each data exchange path, simplifying the configuration process and improving test efficiency.
Solution Approach 2:
Each test domain is equipped with self-contained test compression logic that automatically handles data compression and exchange without requiring external configuration or control. This self-service capability reduces configuration complexity and accelerates the testing process.
Data Source
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AI summary
Embodiments of this application provide a test circuit (03) in a chip and a circuit test method, relate to the field of electronic technologies, and may be applied to EDA software, to resolve problems of winding congestion and complex test configuration in a current test solution. The test circuit (03) transmits input data of a test vector to a data distribution circuit (301) by using an input of a test bus (02), and transmits the input data of the test vector to a scan input channel in a circuit under test (01) by using the data distribution circuit (301). After scan of the circuit under test (01) is completed, output data of the test vector on a scan output channel in the circuit under test (01) is transmitted to an output of the test bus (02) by using the data distribution circuit (301), to complete testing of the circuit under test (01). A dynamic correspondence between the data distribution circuit (301) and the test bus (02) may be configured based on a specific test solution, so that a test resource can be dynamically allocated. In this way, the winding congestion problem can be optimized to a great extent, to reduce test costs, and a configuration process can be simplified to improve test efficiency.