SoC Test Clock Control Using the Functional Clock Path
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Solution Overview
Problem
Conventional test clock generation systems in SoC devices do not drive clock components in test mode, leading to different frequency and voltage margins between test and functional modes, increasing defect rates and reducing chip yield during mass production.
Innovation Solution
A test mode control system generates a test clock through the same path as the functional clock generation path, using a test mode controller and test multiplexer to ensure the same frequency and voltage margins, allowing normal operation testing of clock components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate test clock generation path is used in conventional systems, then test mode operation is enabled, but the frequency and voltage margins differ from functional mode leading to increased defect rates
Solution Approach 1:
The clock management unit is designed to serve dual purposes: functional clock generation during normal operation and test clock generation during testing. The same clock components (PLL, dividers, multiplexers) are used in both modes, ensuring identical frequency and voltage margins. This is achieved by controlling the CMU to operate in test mode while using its existing functional clock generation path, rather than requiring a separate test clock generation path.
Solution Approach 2:
The invention merges the test clock generation function with the functional clock management unit. Instead of having separate test and functional clock paths, the test clock is generated through the same CMU that generates functional clocks. This consolidation ensures that both clock types benefit from the same frequency synthesis and voltage regulation, eliminating the margin discrepancies that cause defects.
2Ease of operation
If clock components are not driven in test mode, then test mode operation is simplified, but comprehensive testing of clock components cannot be performed
Solution Approach 1:
The system dynamically switches between functional mode and test mode by controlling the clock management unit. In test mode, the CMU is configured to generate test clocks while still driving its internal clock components (PLL, dividers, multiplexers). This dynamic operation allows the same hardware to perform both normal clock distribution and comprehensive test coverage without requiring separate static test paths.
Data Source
AI summary
The present disclosure relates to a test mode control system capable of testing a clock component that configures a clock management unit and generating a test clock by driving the clock component that generates a functional clock and a system-on-chip including the same. The test mode control system according to an embodiment of the present disclosure includes: a test mode controller that transmits a clock control signal to a clock source that configures a high-speed domain of a clock management unit in a test mode; and a test multiplexer that transfers a clock control signal input from the test mode controller to the clock source in the test mode and transfers a clock control signal input from a clock control circuit corresponding to the clock source to the clock source in a functional mode.