SoC Test Device Using User-Defined Logic Registers
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Solution Overview
Problem
The increasing complexity of System-on-a-Chip (SoC) devices with multiple integrated cores poses challenges in testing, as existing standards like IEEE 1500 and IEEE 1149.1 require extensive control signals and increased test time, especially when updating test instructions across multiple cores.
Innovation Solution
A test device and method that serially connects test outputs of one core to the inputs of the next, using a register with user-defined logics to determine if test instructions need updating, thereby reducing the number of control signals and test time by allowing parallel testing without altering the Finite State Machine (FSM) of the test controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IEEE 1500 test standard is used with multiple cores integrated into SoC, then fault coverage of SoC device is improved, but test time increases linearly and multiply with number of cores due to extensive wrapper instruction register updates
Solution Approach 1:
The test architecture segments the SoC into multiple independently testable cores, each with its own wrapper and test instruction register. This segmentation allows parallel testing of individual cores while maintaining comprehensive fault coverage, as each core can be tested independently without requiring sequential updates of all wrapper instruction registers across the entire SoC.
Solution Approach 2:
The test instruction register is designed to be pre-loaded with test instructions before the actual testing process begins. This preliminary action allows the testing to proceed without requiring continuous updates of the instruction register during test execution, thereby reducing test time while maintaining the ability to achieve comprehensive fault coverage through pre-planned test sequences.
2Adaptability or versatility
If more cores are integrated into SoC, then functionality and performance are improved, but control signal complexity and test register length increase linearly and multiply
Solution Approach 1:
A universal test controller architecture is implemented that can manage multiple cores using the same control mechanisms and instruction sets. This multi-functional controller can adapt to different core configurations and types, allowing the SoC to integrate varying numbers and types of cores without proportionally increasing control signal complexity, as the same controller infrastructure serves all cores.
Solution Approach 2:
The test architecture introduces a hierarchical dimension to core management, organizing cores into groups or banks that can be managed collectively. This dimensional organization allows the control system to manage multiple cores more efficiently by operating at different levels of abstraction, thereby reducing the apparent complexity of control signals needed to manage a large number of cores.
3Productivity
If parallel connection architecture is used to reduce test time, then testing efficiency is improved, but hardware and manufacturing costs increase
Solution Approach 1:
The architecture merges multiple core test interfaces into a unified parallel testing framework where cores can be tested simultaneously through shared control resources. This merging approach achieves parallel testing efficiency while avoiding the need for completely separate test infrastructure for each core, thereby controlling hardware and manufacturing costs through resource sharing and consolidation.
Data Source
AI summary
A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.