SoC Test Interface Security via Firmware Authorization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

System-on-a-chip (SoC) integrated circuits face security vulnerabilities due to test interfaces like JTAG, which can be exploited by attackers to access and modify firmware, compromising system security.

Innovation Solution

Implementing a test interface that is only enabled when a predetermined authorization code is present, stored in a secure memory, and using encryption processes like AES or DES to scramble and descramble firmware, ensuring the interface is only accessible for authorized debugging and testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a test interface (e.g., JTAG) is provided for debugging and testing the SoC, then ease of operation for developers is improved, but security is worsened as attackers can penetrate the SoC to copy or modify firmware

Engineering Contradiction:

Improvedebugging and testing capabilityVSAvoidsecurity vulnerability to attackers

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by checking the authorization code in firmware before enabling the test interface. During system initialization, the processor executes boot code that verifies whether the firmware contains the correct authorization code. Only after this preliminary verification passes is the test interface enabled, preventing attackers from accessing the interface before security validation occurs.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism - the authorization code verification process - that stands between the test interface and the processor. This intermediary layer validates security credentials before allowing communication through the test interface, effectively mediating access control and blocking unauthorized attempts while permitting legitimate debugging operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If the test interface is always enabled for debugging purposes, then ease of operation is improved, but reliability of security protection is worsened

Engineering Contradiction:

Improveaccessibility of test interfaceVSAvoidsecurity protection against unauthorized access

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent applies dynamics by making the test interface state variable rather than static. The interface transitions between disabled and enabled states based on runtime verification of the authorization code. This dynamic control allows the system to adapt its accessibility - restricted during normal operation for security, but potentially enabled when proper authorization is confirmed, balancing security reliability with operational accessibility.

Inventive Principle:

Principle #15Dynamics

3Object-affected harmful factors

If encryption (AES/DES) is applied to scramble firmware, then security is improved, but device complexity is worsened due to additional descrambler components

Engineering Contradiction:

Improveprotection of firmware from unauthorized accessVSAvoidaddition of descrambler and encryption logic

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by transforming the firmware from plaintext to encrypted form using cryptographic algorithms (AES or DES). This parameter transformation - changing the state of the firmware data - provides strong security protection. The encrypted firmware cannot be read or modified by attackers, and only the authorized processor with the correct decryption keys can restore it to its functional state, significantly enhancing security despite the added complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8601321B2System-on-a-chip (SoC) test interface security

Publication Date: 2013.12.03 MARVELL ASIA PTE LTD

AI summary

A system-on-chip includes first and second memories, a descrambler, and logic. The first memory stores firmware. A first portion of the firmware is scrambled and located at a predetermined address in the first memory. The second memory stores boot code for a processor. In response to the processor being booted, the boot code instructs the processor to read the first portion of the firmware from the predetermined address in the first memory. The descrambler is configured to create a descrambled value by descrambling the first portion of the firmware. The logic is configured to, in response to the descrambled value matching a predetermined authorization code, enable a test interface that allows a device external to the system-on-chip to access the processor through the test interface. The logic is further configured to, in response to the descrambled value not matching the predetermined authorization code, disable the test interface.