SoC Test System With Dynamic Power And Temperature Control
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Solution Overview
Problem
Current test systems for system on chips (SoCs) lack an efficient method to automatically test software functionality, often relying on manual processes and failing to detect software defects effectively, especially in embedded systems where hardware and software interactions are complex.
Innovation Solution
A test system comprising multiple test units, a power supplier, a temperature controller, and an analyzer that applies various test cases, including dynamic voltage and frequency scaling, operation tests, stability tests, and temperature tests, to independently assess each SoC's software-driven performance, determining defects through analysis of driving voltage, current, and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual testing processes are used for SoC software functionality, then testing can be performed with simple equipment, but testing efficiency is low and software defects cannot be detected effectively
Solution Approach 1:
The test system is divided into multiple independent test units, each capable of independently testing one or more SoCs with specific test cases. This segmentation allows parallel testing operations, significantly improving testing efficiency while maintaining manageable complexity through modular design
Solution Approach 2:
Each test unit is designed with multi-functionality to handle various test cases (DVFS, operation, stability, temperature) and can test multiple SoCs simultaneously. The test units can be configured to perform different testing functions, making the system versatile and efficient without requiring separate dedicated systems for each test type
2Loss of time
If multiple test cases are applied to multiple SoCs simultaneously, then testing time is reduced, but power supply management becomes more complex
Solution Approach 1:
The power supplier dynamically adjusts voltage and frequency levels for each test unit based on the specific test case being executed. This dynamic power management allows multiple test cases to run simultaneously with optimized power consumption, reducing overall testing time while the centralized control maintains manageable complexity
Solution Approach 2:
The system implements feedback mechanisms where test results and power consumption data are continuously monitored and used to adjust power supply levels in real-time. This feedback loop enables efficient power management across multiple parallel test operations, reducing testing time while maintaining controlled complexity through automated adjustment
3Speed
If automated test system is implemented, then testing speed increases, but system complexity and cost increase
Solution Approach 1:
The automated test system is segmented into multiple independent test units that can operate in parallel. Each unit is relatively simple in design but the collective system achieves high testing speed through concurrent operations. This segmentation reduces individual unit complexity while maintaining high overall testing speed
Solution Approach 2:
The test units are designed to operate with a degree of autonomy, automatically executing test cases and reporting results without requiring constant manual intervention. This self-service capability increases testing speed while reducing the operational complexity of managing the automated system
Data Source
AI summary
A test system method for testing software of each of a plurality of system on chips (SoCs) are provided. The test system includes: a plurality of test units configured to test the plurality of SoCs according to a plurality of test cases, respectively; a power supplier configured to supply, to each of the plurality of test units, power of a level corresponding to a corresponding test case, among the plurality of test cases; a temperature controller configured to provide, to each of the plurality of test units, a temperature control signal according to the corresponding test case, and to monitor a measurement temperature, provided from each of the plurality of test units, of each of the plurality of SoCs; and an analyzer configured to analyze at least one of a driving voltage, a driving current, and a driving frequency of each of the plurality of SoCs.