SoC Timing Constraint Validation via Formal Property Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for verifying timing constraints in System on a Chip (SoC) designs are manual and error-prone, requiring extensive manual intervention and lengthy simulations, which can lead to inefficiencies and inaccuracies in validating complex semiconductor packages and register-transfer level (RTL) designs.
Innovation Solution
The implementation of formal verification methodologies using a validation control circuitry that automatically selects and validates timing constraints by converting them into assertions and using X propagation to determine valid functional vectors and counterexamples, reducing the need for manual test case selection and simulation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual verification methods are used to validate timing constraints, then verification thoroughness can be maintained, but verification time and complexity increase significantly
Solution Approach 1:
The verification system performs self-validation through automated test case generation and execution. The tool automatically generates test cases from timing constraints, executes them against the RTL design, and validates compliance without requiring manual test case creation or interpretation, enabling the system to verify itself efficiently
Solution Approach 2:
Manual verification processes are replaced with automated computational systems. The patent substitutes human analysts and manual simulation methods with an automated verification tool that uses formal methods and algorithmic test case generation to validate timing constraints, eliminating the need for mechanical manual intervention
2Reliability
If manual test case selection is performed, then test case relevance can be ensured, but the process becomes labor-intensive and error-prone
Solution Approach 1:
The system automatically generates test cases from timing constraints without human intervention. The verification tool extracts timing relationships from constraint specifications and autonomously creates appropriate test scenarios, eliminating manual test case selection while maintaining accuracy through formal methods
Solution Approach 2:
The patent introduces an automated verification tool as an intermediary between timing constraints and validation results. This intermediary automatically translates timing constraints into test cases and evaluates compliance, serving as a mediator that eliminates the need for direct manual analysis while ensuring systematic verification
3Measurement precision
If extensive manual simulation is conducted, then comprehensive coverage can be achieved, but simulation time becomes prohibitively long
Solution Approach 1:
The verification system autonomously generates and executes test cases without requiring extensive manual simulation campaigns. By automatically deriving test cases from timing constraints and executing them systematically, the tool achieves comprehensive coverage while minimizing simulation time through intelligent test selection and automated execution
Solution Approach 2:
The patent applies targeted verification by generating only the necessary test cases required to validate timing constraints, rather than performing exhaustive manual simulation of all possible scenarios. This selective approach achieves sufficient verification coverage with significantly reduced simulation time by focusing on critical timing paths
Data Source
AI summary
Methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. An example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (SoC) architecture, obtain a timing assertion associated with the SoC architecture, determine, using a formal property verification (FPV) tool, valid functional vectors and counter examples for the SoC architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.