Trace-Based SoC Security Subsystem for Unauthorized Code Execution Detection
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Solution Overview
Problem
Integrated circuit devices, such as SoCs, face vulnerabilities to attacks that compromise their security, allowing unauthorized code execution and unbridled access to device data and functionality, with attackers potentially bypassing secure boot mechanisms and cloud verifications.
Innovation Solution
A hardware-level security subsystem is integrated into the SoC architecture, featuring a hardened hardware root of trust, isolated execution environment, and execution verification engine, enabling remote attestation and execution verification to detect and prevent various attacks, including fault injections and software exploitation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware root of trust is implemented in the SoC, then security against malware tampering is improved, but device complexity increases
Solution Approach 1:
The security subsystem is implemented as a separate, isolated module within the SoC architecture, distinct from the main CPU and memory subsystems. This segmentation allows the root of trust to be hardened independently while minimizing its impact on overall device complexity. The execution verification module and remote attestation module are further divided into separate functional units that can be independently configured and activated.
Solution Approach 2:
The security subsystem acts as an intermediary between the CPU subsystem and external verification systems. It provides a controlled interface for remote attestation and execution verification without requiring direct access to critical internal components. The trace blocks and system interconnect serve as intermediaries that allow monitoring and verification while maintaining isolation.
2Reliability
If execution verification is performed continuously, then detection of unauthorized code execution is improved, but use of energy increases
Solution Approach 1:
The execution verification can be configured to operate periodically rather than continuously, with the verification core checking execution traces at defined intervals. The system supports both continuous verification mode and periodic sampling mode, allowing energy consumption to be adjusted based on security requirements. Remote attestation can be triggered by specific events or time intervals rather than running constantly.
Solution Approach 2:
The verification core can perform partial verification by checking only critical execution traces or specific address ranges rather than analyzing every instruction. The system allows selective verification of important code sections while reducing or skipping verification in less critical areas, thereby reducing overall energy consumption while maintaining adequate security detection capability.
3Measurement precision
If remote attestation is implemented, then verification of device integrity is improved, but device complexity increases
Solution Approach 1:
The security subsystem is designed to provide multiple security functions including remote attestation, execution verification, and cryptographic operations through a unified architecture. The same trace blocks, verification core, and cryptographic modules serve multiple purposes, reducing overall device complexity compared to implementing separate dedicated systems for each function.
Solution Approach 2:
The remote attestation functionality is merged with the execution verification module, allowing both functions to share common infrastructure including the verification core, trace buffer, and system interconnect interfaces. The cryptographic functions are integrated into the same security subsystem that handles attestation, consolidating multiple security features into a single coherent unit rather than separate components.
Data Source
AI summary
Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.