On-Chip Transaction Tracing for SoC Debugging
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Solution Overview
Problem
The integration of multiple core devices onto a single System-on-Chip (SoC) reduces the ability of external debugging tools to access and trace transactions on internal buses, due to lower off-chip data rates and increased data volume, making it impractical to trace every transaction effectively.
Innovation Solution
A method for tracing transactions on an integrated circuit chip that involves extracting transactions from interconnect circuitry, applying filtering and triggering conditions to address, data, and response signals, and storing them in respective buffers only if they meet these conditions, with the ability to discard or retain transactions based on these criteria, and outputting them when the triggering condition is met, while managing buffer overflow and utilizing pre-buffering for data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all transactions are traced and stored in buffers until filtering/triggering conditions are met, then complete transaction data is captured for debugging, but extensive storage allocation is required
Solution Approach 1:
The patent applies preliminary action by performing address phase filtering before the data phase is complete. The filtering condition is evaluated during the address phase, and only transactions meeting the condition proceed to data phase buffering. This prevents storage of data phases for transactions that will ultimately be filtered out, reducing required storage allocation while maintaining debugging accuracy for relevant transactions.
2Measurement precision
If filtering condition is applied only after transaction completion, then accurate transaction-level filtering is achieved, but all intermediate phases must be stored extensively
Solution Approach 1:
The patent segments the filtering process into two stages: address phase filtering and data phase filtering. The address phase filtering provides early elimination of non-matching transactions, while the data phase filtering ensures precise transaction-level accuracy. This segmentation allows the system to achieve both filtering accuracy and reduced storage requirements by discarding non-matching transactions early in their lifecycle.
3Productivity
If multiple concurrent transactions are traced, then comprehensive system monitoring is achieved, but storage requirements increase proportionally
Solution Approach 1:
The patent applies preliminary action by evaluating filtering conditions on the address phase of multiple concurrent transactions before their data phases are fully executed. This allows the system to monitor many concurrent transactions while discarding non-matching ones early, preventing the need to allocate storage proportional to all concurrent transactions regardless of their relevance to debugging conditions.
Data Source
AI summary
A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.