SoC Transaction Controller Using Sequence Counters for In-Order Packet Delivery
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Solution Overview
Problem
Conventional system-on-chip (SoC) controllers require multiple data buffers to order out-of-order transactions, leading to increased area and power consumption.
Innovation Solution
A transaction controller using sequence and ordering counters to record and transmit data packets in-order, eliminating the need for multiple data buffers by determining the correct order based on transaction identifiers and sequence values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple data buffers are used to queue data packets for each virtual master, then transactions can be ordered correctly, but area and power consumption increase significantly
Solution Approach 1:
The patent merges multiple separate data buffers into a single shared data buffer that serves all virtual masters. Instead of having dedicated buffers for each virtual master, the controller uses one buffer with a pointer mechanism to manage data packets from different virtual masters sequentially, thereby reducing the total area required while maintaining correct transaction ordering.
Solution Approach 2:
The single data buffer is designed to be universal, handling data packets from any virtual master through a shared interface. The controller uses virtual master identifiers and pointer management to direct operations to the appropriate data packets within the same buffer, making the buffer multi-functional rather than dedicated to a single virtual master.
2Reliability
If multiple data buffers are used to queue data packets for each virtual master, then transactions can be ordered correctly, but power consumption increases
Solution Approach 1:
By combining multiple buffers into one, the controller reduces the number of buffer management operations, memory access conflicts, and control logic required. This consolidation decreases the overall power consumption of the controller while preserving the ability to correctly order transactions through pointer-based management.
3Area of stationary object
If a single data buffer is used for all virtual masters, then area and power consumption are reduced, but managing out-of-order transactions becomes more complex
Solution Approach 1:
The patent introduces a pointer as an intermediary element between the controller and the single data buffer. This pointer acts as a mediator that tracks the position of data packets from different virtual masters, enabling the controller to manage the unified buffer efficiently without direct complex addressing of individual buffer regions for each virtual master.
Solution Approach 2:
The patent replaces the mechanical/physical separation of multiple buffers with a logical/algorithmic management system using pointers and virtual master identifiers. Instead of physically separating data packets into different memory regions, the system uses software-based pointer management to organize and retrieve data packets in the correct order from a unified memory structure.
Data Source
AI summary
A transaction controller orders transactions between a master device and a slave device, where the transactions may be received out-of-order. First and second transactions have respective first and second sets of data packets. The transaction controller includes a transaction table, a first ordering counter, and a first sequence counter having first and second values when the first and second transactions are initiated. The first and second values are stored in the transaction table based on first and second transaction identifiers (TIDs) that are associated with the first and second transactions. The transaction controller determines, based on the second value, the second TID, and a current value of the first ordering counter, whether the first and second sets of data packets were received out-of-order. Based on the determination, the second set of data packets is transmitted to the master device after the first set of data packets.